DK-DEV-4SGX530N Altera, DK-DEV-4SGX530N Datasheet - Page 23

• Manufacturer Part Number: DK-DEV-4SGX530N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IV GXr
• Type: FPGAr

Specifications of DK-DEV-4SGX530N

• Contents: Board, Cable, Documentation, Power Supply
• For Use With/related Products: Stratix® IV GX
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2714

Chapter 2: Board Components
Configuration, Status, and Setup Elements
August 2010 Altera Corporation
Status Elements
f
Table 2–8. Flash Memory Map (Part 2 of 2)
There are two pages reserved for the FPGA configuration data. The factory hardware
page is considered page 0 and is loaded if the rotary switch is in position 0 and when
either power is cycled or the reset configuration push-button switch (S1) is pressed.
The user hardware page is considered page 1 and is loaded if the rotary switch is in
position 1 and when either power is cycled or the reset configuration push-button
switch (S1) is pressed.
FPGA Programming over External USB-Blaster
The JTAG programming header provides another method for configuring the FPGA
(U13) using an external USB-Blaster device with the Quartus II Programmer running
on a PC. The external USB-Blaster is connected to the board through the JTAG
connector (J8). The JTAG DIP switch (SW6) allows the MAX II CPLD device to be
removed from the JTAG chain so that the FPGA is the only device on the JTAG chain.
For more information on the following topics, refer to the respective documents:
■
■
■
The development board includes status LEDs. This section describes the status
elements.
Factory Software
zipfs — HTML, Web Content
User Hardware
Factory Hardware
PFL Option Bits
Board Information
Ethernet Option Bits
User Design Reset Vector
Board Update Portal, refer to the
PFL design, refer to the
PFL megafunction, refer to
II Software.
Name
Stratix IV GX FPGA Development Kit User
AN 386: Using the Parallel Flash Loader with the Quartus
Stratix IV GX FPGA Development Kit User
Size (Kbyte)
Stratix IV GX FPGA Development Board Reference Manual
12,288
12,288
8,192
8,192
32
32
32
32
0x0181.FFFF
0x00C2.0000
0x00C1.FFFF
0x0002.0000
0x0202.0000
0x0182.0000
0x0001.8000
0x0001.0000
0x0000.8000
0x0000.0000
0x0001.7FFF
0x0000.7FFF
0x0281.FFFF
0x0201.FFFF
0x0001.FFFF
0x0000.FFFF
Address
Guide.
Guide.
2–15