DK-DEV-4SGX530N Altera, DK-DEV-4SGX530N Datasheet - Page 18

• Manufacturer Part Number: DK-DEV-4SGX530N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IV GXr
• Type: FPGAr

Specifications of DK-DEV-4SGX530N

• Contents: Board, Cable, Documentation, Power Supply
• For Use With/related Products: Stratix® IV GX
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2714

2–10
Table 2–6. MAX II CPLD EPM2210 System Controller Device Pin-Out (Part 4 of 5)
Stratix IV GX FPGA Development Board Reference Manual
FPGA_nSTATUS
FPGA_nCONFIG
FPGA_CONF_DONE
SENSE_SCK
SENSE_SDI
SENSE_SDO
SENSE_CS0n
SENSE_CS1n
SENSE_ADN_F0
SENSE_SMB_CLK
SENSE_SMB_DATA
OVERTEMPn
ALERTn
PHASE_0
PHASE_90
PHASE_135
PHASE_270
MAX_ERROR
MAX_LOAD
MAX_CONF_DONEn
USB_LED
HSMA_PRSNTn
HSMB_PRSNTn
MAX_DIP
USB_DISABLEn
LCD_PWRMON
FAN_FORCE_ON
CLK_SEL
CLK_ENABLE
PGM3
PGM2
PGM1
PGM0
RESET_CONFIGn
CPU_RESETn
SRAM_MODE
SRAM_ZZ
CLK50_EN
CLK100_EN
Schematic Signal
Name
I/O Standard
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
Pin Number
EPM2210
G14
G12
G16
E15
F12
J16
J13
F15
L14
M3
M2
M9
H3
N1
N2
R1
R4
P5
R7
P8
G3
G2
R5
P7
N7
K1
K2
P4
T2
J1
L5
L4
L3
T6
T7
T5
J3
J4
J2
EP4SGX230
Pin Number
AW35
AW36
AB31
AH32
AV35
AE28
W34
V28
H35
G35
V34
J35
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
FPGA configuration ready
FPGA configuration active
FPGA configuration done
Power monitor SPI clock
Power monitor SPI data in
Power monitor SPI data out
Power monitor 0 chip select
Power monitor 1 chip select
Power monitor frequency
Temperature monitor SMB clock
Temperature monitor SMB data
Temperature monitor over-temperature indicator
Temperature monitor alert
Power clock 0 degrees
Power clock 90 degrees
Power clock 135 degrees
Power clock 270 degrees
FPGA configuration error LED
FPGA configuration active LED
FPGA configuration done LED
Embedded USB-Blaster active
HSMC port A present
HSMC port B present
DIP-reserved
DIP-embedded USB-Blaster disable
DIP-MAX2 LCD drive enable
DIP-force fan on switch
DIP-clock select SMA or oscillator
DIP-clock oscillator enable
Rotary switch input
Rotary switch input
Rotary switch input
Rotary switch input
Force FPGA configuration push-button switch
Reset push-button switch
SRAM mode
SRAM sleep mode
50 MHz oscillator enable
100 MHz oscillator enable
MAX II CPLD EPM2210 System Controller
Description
August 2010 Altera Corporation
Chapter 2: Board Components