DK-DEV-4SGX530N Altera, DK-DEV-4SGX530N Datasheet - Page 58

• Manufacturer Part Number: DK-DEV-4SGX530N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IV GXr
• Type: FPGAr

Specifications of DK-DEV-4SGX530N

• Contents: Board, Cable, Documentation, Power Supply
• For Use With/related Products: Stratix® IV GX
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2714

2–50
Table 2–46. DDR3 Bottom Port Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 4)
Stratix IV GX FPGA Development Board Reference Manual
U5, U12, U18, U24 pin K3
U5, U12, U18, U24 pin L2
U5, U12, U18, U24 pin L3
U5, U12, U18, U24 pin K1
U5, U12, U18, U24 pin K9
U5, U12, U18, U24 pin J7
U5, U12, U18, U24 pin K7
U5.E3
U5.F7
U5.F2
U5.F8
U5.H3
U5.H8
U5.G2
U5.H7
U5.E7
U5.F3
U5.G3
U5.D7
U5.C3
U5.C8
U5.C2
U5.A7
U5.A2
U5.B8
U5.A3
U5.D3
U5.C7
U5.B7
U12.E3
U12.F7
U12.F2
U12.F8
U12.H3
U12.H8
U12.G2
U12.H7
U12.E7
Board Reference
Column address select
Chip select
Write enable
Termination enable
Clock enable
Clock P
Clock N
Data bus byte lane 0
Data bus byte lane 0
Data bus byte lane 0
Data bus byte lane 0
Data bus byte lane 0
Data bus byte lane 0
Data bus byte lane 0
Data bus byte lane 0
Write mask byte lane 0
Data strobe P byte lane 0
Data strobe N byte lane 0
Data bus byte lane 1
Data bus byte lane 1
Data bus byte lane 1
Data bus byte lane 1
Data bus byte lane 1
Data bus byte lane 1
Data bus byte lane 1
Data bus byte lane 1
Write mask byte lane 1
Data strobe P byte lane 1
Data strobe N byte lane 1
Data bus byte lane 2
Data bus byte lane 2
Data bus byte lane 2
Data bus byte lane 2
Data bus byte lane 2
Data bus byte lane 2
Data bus byte lane 2
Data bus byte lane 2
Write mask byte lane 2
Description
Schematic Signal
DDR3BOT_DQS_P0
DDR3BOT_DQS_N0
DDR3BOT_DQS_P1
DDR3BOT_DQS_N1
DDR3BOT_CASn
DDR3BOT_CK_P
DDR3BOT_CK_N
DDR3BOT_DQ10
DDR3BOT_DQ11
DDR3BOT_DQ12
DDR3BOT_DQ13
DDR3BOT_DQ14
DDR3BOT_DQ15
DDR3BOT_DQ16
DDR3BOT_DQ17
DDR3BOT_DQ18
DDR3BOT_DQ19
DDR3BOT_DQ20
DDR3BOT_DQ21
DDR3BOT_DQ22
DDR3BOT_DQ23
DDR3BOT_CSn
DDR3BOT_WEn
DDR3BOT_ODT
DDR3BOT_CKE
DDR3BOT_DQ0
DDR3BOT_DQ1
DDR3BOT_DQ2
DDR3BOT_DQ3
DDR3BOT_DQ4
DDR3BOT_DQ5
DDR3BOT_DQ6
DDR3BOT_DQ7
DDR3BOT_DM0
DDR3BOT_DQ8
DDR3BOT_DQ9
DDR3BOT_DM1
DDR3BOT_DM2
Name
1.5-V SSTL Class I
I/O Standard
August 2010 Altera Corporation
Chapter 2: Board Components
Stratix IV GX
Pin Number
Device
AW20
AW19
AM14
AM13
AW14
AW11
AW12
AW13
AW16
AV19
AN20
AU20
AN14
AR14
AN13
AP14
AP13
AR13
AU12
AV14
AU14
AV11
AU11
AV13
AN16
AV16
AP17
AR17
AU15
AU16
AE20
AF20
AL14
AL13
AT13
AT12
AT16
AT15
Memory