DK-DEV-4SGX530N Altera, DK-DEV-4SGX530N Datasheet - Page 34
![no-image](/images/manufacturer_photos/0/0/40/altera_sml.jpg)
DK-DEV-4SGX530N
Manufacturer Part Number
DK-DEV-4SGX530N
Description
KIT DEVELOPMENT STRATIX IV
Manufacturer
Altera
Series
Stratix® IV GXr
Type
FPGAr
Datasheets
1.DK-DEV-4SGX530N.pdf
(57 pages)
2.DK-DEV-4SGX530N.pdf
(84 pages)
3.DK-DEV-4SGX530N.pdf
(1 pages)
Specifications of DK-DEV-4SGX530N
Contents
Board, Cable, Documentation, Power Supply
For Use With/related Products
Stratix® IV GX
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2714
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
2–26
Table 2–23. User-Defined Push-Button Switch Schematic Signal Names and Functions
Table 2–24. User-Defined Push-Button Switch Component Reference and Manufacturing Information
Table 2–25. User-Defined DIP Switch Schematic Signal Names and Functions
Stratix IV GX FPGA Development Board Reference Manual
S2
S3
S4
S5
S2 to S5
SW3.1
SW3.2
SW3.3
SW3.4
SW3.5
SW3.6
SW3.7
SW3.8
Board Reference
Board Reference
Board Reference
User-Defined DIP Switches
User-Defined DIP switch connected to
FPGA device. When the switch is in
the OPEN or OFF position, a logic 1 is
selected. When the switch is in the
CLOSED or ON position, a logic 0 is
selected.
User-Defined push-button switch
Push-Button switch
Board reference S2 is the CPU reset push-button switch, CPU_RESETn, which is an input
to both the Stratix IV GX device and MAX II CPLD EPM2210 System Controller. The
CPU_RESETn is intended to be the master reset signal for the FPGA design loaded into
the Stratix IV GX device. The CPU_RESETn signal must be enabled within the Quartus II
software for this reset function to work. Otherwise, the CPU_RESETn acts as a regular
I/O pin. When enabled in the Quartus II software, and then pulled high on the board,
this switch resets every register within the FPGA.
Table 2–23
corresponding Stratix IV GX device pin numbers.
Table 2–24
manufacturing information.
Board reference S6 is an 8-pin DIP switch. The switches in S6 are user-defined, and are
provided for additional FPGA input control. There is no board-specific function for
these switches.
Table 2–25
corresponding Stratix IV GX pin numbers.
Description
Description
Description
lists the user-defined push-button switch schematic signal names and their
lists the user-defined push-button switch component reference and the
lists the user-defined DIP switch schematic signal names and their
Panasonic Corporation
Manufacturer
Schematic Signal
USER_DIPSW0
USER_DIPSW1
USER_DIPSW2
USER_DIPSW3
USER_DIPSW4
USER_DIPSW5
USER_DIPSW6
USER_DIPSW7
CPU_RESETn
Signal Name
Schematic
USER_PB2
USER_PB1
USER_PB0
Name
EVQPAC07K
Manufacturer
Part Number
I/O Standard
I/O Standard
2.5-V
2.5-V
August 2010 Altera Corporation
Chapter 2: Board Components
Stratix IV GX Device
Stratix IV GX Device
General User Input/Output
www.panasonic.com
Manufacturer
Pin Number
Pin Number
Website
AC35
AN35
AG34
AG31
AK35
AL35
M34
W32
G33
K35
V34
J34