DK-DEV-4SGX530N Altera, DK-DEV-4SGX530N Datasheet - Page 65

• Manufacturer Part Number: DK-DEV-4SGX530N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IV GXr
• Type: FPGAr

Specifications of DK-DEV-4SGX530N

• Contents: Board, Cable, Documentation, Power Supply
• For Use With/related Products: Stratix® IV GX
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2714

Chapter 2: Board Components
Memory
Table 2–51. QDRII+ Top Port 0 Component Reference and Manufacturing Information
Table 2–52. QDRII+ Top Port 1 Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 3)
August 2010 Altera Corporation
U22
U7.A10
U7.A3
U7.A9
U7.R7
U7.R5
U7.R4
U7.R3
U7.P8
U7.P7
U7.P5
U7.P4
U7.N7
U7.N6
U7.N5
U7.C7
U7.C5
U7.B8
U7.B4
Board Reference
Reference
Board
QDRII+ Top Port 1
QDRII+, 4 M × 18, 400 MHZ
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Table 2–51
information.
The QDRII+ top port 1 consists of a single QDRII+ burst-of-4 SRAM, providing
4 Mbyte with an 18-bit read data bus and an 18-bit write data bus.
This memory interface is designed to run between 120 MHz, the minimum frequency
for this device, and 400 MHz for a maximum theoretical bandwidth of over 14.4 Gbps
for reading and 14.4 Gbps for writing. The internal bus in the FPGA is typically 2 or 4
times the width at full rate or half rate respectively. For example, a 400 MHz 18-bit
interface becomes a 200 MHz 72 bit bus.
Table 2–52
The signal names and types are relative to the Stratix IV GX device in terms of I/O
setting and direction.
Description
Description
lists the QDRII+ top port 0 component reference and manufacturing
lists the QDRII+ top port 1 pin assignments, signal names, and functions.
Cypress
NEC
Samsung
Manufacturer
Schematic Signal Name
QDR2TOP1_A19
QDR2TOP1_A18
QDR2TOP1_A17
QDR2TOP1_A16
QDR2TOP1_A15
QDR2TOP1_A14
QDR2TOP1_A13
QDR2TOP1_A12
QDR2TOP1_A11
QDR2TOP1_A10
QDR2TOP1_A9
QDR2TOP1_A8
QDR2TOP1_A7
QDR2TOP1_A6
QDR2TOP1_A5
QDR2TOP1_A4
QDR2TOP1_A3
QDR2TOP1_A2
uPD44647186AF5-E22-FQ1
CY7C2563KV18-400BZXC
K7S3218U4C-EC40
Stratix IV GX FPGA Development Board Reference Manual
Manufacturing
Part Number
1.5-V HSTL Class I
I/O Standard
www.samsung.com
www.cypress.com
Manufacturer
www.nec.com
Stratix IV GX
Pin Number
Website
Device
M19
G20
R18
D17
G18
G19
B17
E17
P18
L19
C18
A18
A17
F20
J18
F18
F17
F16
2–57