MCIMX53-START Freescale Semiconductor, MCIMX53-START Datasheet - Page 110

KIT DEVELOPMENT I.MX53

MCIMX53-START

Manufacturer Part Number
MCIMX53-START
Description
KIT DEVELOPMENT I.MX53
Manufacturer
Freescale Semiconductor
Series
i.MX53r
Type
MCUr
Datasheets

Specifications of MCIMX53-START

Contents
Board
Silicon Manufacturer
Freescale
Core Architecture
ARM
Core Sub-architecture
Cortex - A8
Silicon Core Number
I.MX5
Silicon Family Name
I.MX53
Peak Reflow Compatible (260 C)
Yes
Rohs Compliant
Yes
Leaded Process Compatible
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
i.MX53
Lead Free Status / Rohs Status
Supplier Unconfirmed

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Electrical Characteristics
4.7.9
The LVDS interface complies with TIA/EIA 644-A standard. For more details, see TIA/EIA STANDARD
644-A, “Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits”.
4.7.10
This section describes the timing electrical information of the MediaLB Controller module.
Figure 60
MediaLB controller timing characteristics.
110
15
DISP_CS_DOWN is predefined in REGISTER.
Display RS down time
and
LVDS Display Bridge (LDB) Module Parameters
MediaLB (MLB) Controller AC Timing Electrical Specifications
Figure 61
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1
show the timing of MediaLB Controller, and
Figure 61. MediaLB Pulse Width Variation Timing
Tdicdcs
Figure 60. MediaLB Timing
=
(
T DI_CLK
×
ceil
)
DISP_CS_DOWN_#
-------------------------------------------------- -
DI_CLK_PERIOD
Table 63
and
Table 64
Freescale Semiconductor
lists the

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