MCIMX53-START Freescale Semiconductor, MCIMX53-START Datasheet - Page 4

• Manufacturer Part Number: MCIMX53-START
• Description: KIT DEVELOPMENT I.MX53
• Manufacturer: Freescale Semiconductor
• Series: i.MX53r
• Type: MCUr

Specifications of MCIMX53-START

• Contents: Board
• Silicon Manufacturer: Freescale
• Core Architecture: ARM
• Core Sub-architecture: Cortex - A8
• Silicon Core Number: I.MX5
• Silicon Family Name: I.MX53
• Peak Reflow Compatible (260 C): Yes
• Rohs Compliant: Yes
• Leaded Process Compatible: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: i.MX53
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Introduction
The i.MX53xA system is built around the following system on chip interfaces:
The i.MX53xA makes use of dedicated hardware accelerators to achieve state-of-the-art multimedia
performance. The use of hardware accelerators provides both high performance and low power
consumption while freeing up the CPU core for other tasks.
The i.MX53xA incorporates the following hardware accelerators:
The i.MX53xA includes the following interfaces to external devices:
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— All EIM pins are muxed on other interfaces (data with NFC pins). I/O muxing logic selects
— Samsung OneNAND™ and managed NAND including eMMC up to rev 4.4 (in muxed I/O
64-bit AMBA AXI v1.0 bus—used by ARM platform, multimedia accelerators (such as VPU, IPU,
GPU3D, GPU2D) and the external memory controller (EXTMC) operating at 200 MHz.
32-bit AMBA AHB 2.0 bus—used by the rest of the bus master peripherals operating at 133 MHz.
32-bit IP bus—peripheral bus used for control (and slow data traffic) of the most system peripheral
devices operating at 66 MHz.
VPU, version 3—video processing unit
GPU3D—3D graphics processing unit, OpenGL ES 2.0, version 3, 33 Mtri/s, 200 Mpix/s, and
800 Mpix/s z-plane performance, 256 Kbyte RAM memory
GPU2D—2D graphics accelerator, OpenVG 1.1, version 1, 200 Mpix/s performance,
IPU, version 3M—image processing unit
ASRC—asynchronous sample rate converter
Hard disk drives:
— PATA, up to U-DMA mode 5, 100 MByte/s
— SATA I, 1.5 Gbps
Displays:
— Five interfaces available. Total rate of all interfaces is up to 180 Mpixels/s, 24 bpp. Up to two
— Two parallel 24-bit display ports. The primary port is up to 165 Mpix/s (for example,
— LVDS serial ports: one dual channel port up to 165 Mpix/s or two independent single channel
— TV-out/VGA port up to 150 Mpix/s (for example, 1080p60).
Camera sensors:
— Two parallel 20-bit camera ports. Primary up to 180-MHz peak clock frequency, secondary up
EIM port, as primary muxing at system boot.
mode)
interfaces may be active at once.
UXGA @ 60 Hz).
ports up to 85 MP/s (for example, WXGA @ 60 Hz) each.
to 120-MHz peak clock frequency.
Not all interfaces are available simultaneously, depending on I/O
multiplexer configuration.
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1
NOTE
Freescale Semiconductor