MCIMX53-START Freescale Semiconductor, MCIMX53-START Datasheet - Page 25

• Manufacturer Part Number: MCIMX53-START
• Description: KIT DEVELOPMENT I.MX53
• Manufacturer: Freescale Semiconductor
• Series: i.MX53r
• Type: MCUr

Specifications of MCIMX53-START

• Contents: Board
• Silicon Manufacturer: Freescale
• Core Architecture: ARM
• Core Sub-architecture: Cortex - A8
• Silicon Core Number: I.MX5
• Silicon Family Name: I.MX53
• Peak Reflow Compatible (260 C): Yes
• Rohs Compliant: Yes
• Leaded Process Compatible: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: i.MX53
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Freescale Semiconductor
• NVCC_SRTC_POW should remain powered ON continuously, to maintain internal real-time
• The VCC should be powered ON together, or any time after NVCC_SRTC_POW.
• NVCC_CKIH should be powered ON after VCC is stable and before other IO supplies
• IO Supplies (NVCC_xxx) below or equal to 2.8 V nom./3.1 V max. should not precede
• IO Supplies (NVCC_xxx) above 2.8 V nom./3.1 V max. should be powered ON only after
• In case VDD_DIG_PLL and VDD_ANA_PLL are powered ON from internal voltage regulator
• VDD_REG supply is required to be powered ON to enable DDR operation. It must be powered
• VDDA and VDDAL1 can be powered ON anytime before POR_B, regardless of any other
• VDDGP can be powered ON anytime before POR_B, regardless of any other power signal.
• VP and VPH can be powered up together, or anytime after, the VCC. VP and VPH should come
• TVDAC_DHVDD and TVDAC_AHVDDRGB should be powered from the same regulator.
clock status. Otherwise, it has to be powered ON together with VCC, or preceding VCC.
(NVCC_xxx) are powered ON.
NVCC_CKIH. They can start powering ON during NVCC_CKIH ramp-up, before it is
stabilized. Within this group, the supplies can be powered-up in any order.
NVCC_CKIH is stable.
(default case for i.MX53), there are no related restrictions on VDD_REG, as it is used as their
internal regulators power source.
If VDD_DIG_PLL and VDD_ANA_PLL are powered on externally, to reduce current leakage
during the power-up, it is recommended to activate the VDD_REG before or at the same time
with VDD_DIG_PLL and VDD_ANA_PLL. If this sequencing is not possible, make sure that
the 2.5 V VDD_REG supply shut-off output impedance is higher than 1 kΩ when it is inactive.
on after VCC and before NVCC_EMI_DRAM. The sequence should be:
power signal.
before POR.
This is due to ESD diode protection circuit, that may cause current leakage if one of the supplies
is powered ON before the other.
The POR_B input must be immediately asserted at power-up and remain
asserted until after the last power rail reaches its working voltage.
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1
VCC →VDD_REG →NVCC_EMI_DRAM
NOTE
Electrical Characteristics
25