MCIMX53-START Freescale Semiconductor, MCIMX53-START Datasheet - Page 116

• Manufacturer Part Number: MCIMX53-START
• Description: KIT DEVELOPMENT I.MX53
• Manufacturer: Freescale Semiconductor
• Series: i.MX53r
• Type: MCUr

Specifications of MCIMX53-START

• Contents: Board
• Silicon Manufacturer: Freescale
• Core Architecture: ARM
• Core Sub-architecture: Cortex - A8
• Silicon Core Number: I.MX5
• Silicon Family Name: I.MX53
• Peak Reflow Compatible (260 C): Yes
• Rohs Compliant: Yes
• Leaded Process Compatible: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: i.MX53
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Electrical Characteristics
The user must use level shifters for 5.0 V compatibility on the ATA interface. The i.MX53xA PATA
interface is 3.3 V compatible.
The use of bus buffers introduces delay on the bus and skew between signal lines. These factors make it
difficult to operate the bus at the highest speed (UDMA-5) when bus buffers are used. If fast UDMA mode
operation is needed, this may not be compatible with bus buffers.
Another area of attention is the slew rate limit imposed by the ATA specification on the ATA bus.
According to this limit, any signal driven on the bus should have a slew rate between 0.4 and 1.2 V/ns with
a 40 pF load. Not many vendors of bus buffers specify slew rate of the outgoing signals.
When bus buffers are used, the ata_data bus buffer is special. This is a bidirectional bus buffer, so a
direction control signal is needed. This direction control signal is ata_buffer_en. When its high, the bus
should drive from host to device. When its low, the bus should drive from device to host. Steering of the
signal is such that contention on the host and device tri-state busses is always avoided.
In the timing equations, some timing parameters are used. These parameters depend on the
implementation of the i.MX53xA PATA interface on silicon, the bus buffer used, the cable delay and
cable skew.
116
tskew1
tskew2
tskew3
Name
ti_dh
ti_ds
tsui
tco
tsu
thi
T
Set-up time ata_data to ata_iordy edge (UDMA-in only)
Propagation delay bus clock L-to-H to
Set-up time ata_data to bus clock L-to-H
Max difference in propagation delay bus clock L-to-H to any of following signals
Max difference in buffer propagation delay for any of following signals:
Max difference in buffer propagation delay for any of following signals ata_iordy,
Bus clock period (AHB_CLK_ROOT)
Hold time ata_iordy edge to ata_data (UDMA-in only)
ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack,
ata_data, ata_buffer_en
Set-up time ata_iordy to bus clock H-to-L
Hold time ata_iordy to bus clock H to L
ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack,
ata_data (write), ata_buffer_en
ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack,
ata_data (write), ata_buffer_en
ata_data (read)
Table 70
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1
shows ATA timing parameters.
Table 70. PATA Timing Parameters
Description
UDMA0, UDMA1, UDMA2, UDMA3, UDMA4
UDMA2, UDMA3
UDMA0
UDMA1
UDMA4
UDMA5
UDMA5
Peripheral clock frequency
(7.5 ns for 133 MHz clock)
Contributing Factor
Freescale Semiconductor
Transceiver
Transceiver
12.0 ns
Value/
5.0 ns
4.6 ns
8.5 ns
8.5 ns
2.5 ns
15 ns
10 ns
7 ns
5 ns
4 ns
7 ns
1