MCIMX53-START Freescale Semiconductor, MCIMX53-START Datasheet - Page 12

• Manufacturer Part Number: MCIMX53-START
• Description: KIT DEVELOPMENT I.MX53
• Manufacturer: Freescale Semiconductor
• Series: i.MX53r
• Type: MCUr

Specifications of MCIMX53-START

• Contents: Board
• Silicon Manufacturer: Freescale
• Core Architecture: ARM
• Core Sub-architecture: Cortex - A8
• Silicon Core Number: I.MX5
• Silicon Family Name: I.MX53
• Peak Reflow Compatible (260 C): Yes
• Rohs Compliant: Yes
• Leaded Process Compatible: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: i.MX53
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Modules List
12
Mnemonic
IOMUXC
OWIRE
PWM-1
PWM-2
Block
PATA
MLB
KPP
LDB
IPU
IOMUX Control
Image
Processing Unit
Keypad Port
LVDS Display
Bridge
One-Wire
Interface
Parallel ATA
Pulse Width
Modulation
bus—MediaLB
Block Name
Media local
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1
Table 2. i.MX53xA Digital and Analog Blocks (continued)
System
Control
Peripherals
Multimedia
Peripherals
Connectivity
Peripherals
Connectivity
Peripherals
Connectivity
Peripherals
Connectivity
Peripherals
Connectivity
Peripherals
Connectivity/
Subsystem
Peripherals
Multimedia
This module enables flexible I/O multiplexing. Each I/O pad has default as
well as several alternate functions. The alternate functions are software
configurable.
Version 3M IPU enables connectivity to displays, relevant processing and
synchronization. It supports two display ports and two camera ports,
through the following interfaces:
The processing includes:
The KPP supports an 8 × 8 external keypad matrix. The KPP features are
as follows:
LVDS display bridge is used to connect the IPU (image processing unit) to
external LVDS display interface. LDB supports two channels; each channel
has following signals:
On-chip differential drivers are provided for each pair.
The MLB interface module provides a link to a MOST
One-wire support provided for interfacing with an on-board EEPROM, and
smart battery interfaces, for example, Dallas DS2502.
The PATA block is a AT attachment host interface. Its main use is to interface
with hard disk drives and optical disc drives. It interfaces with the ATA-6
compliant device over a number of ATA signals. It is possible to connect a
bus buffer between the host side and the device side.
The pulse-width modulator (PWM) has a 16-bit counter and is optimized to
generate sound from stored sample audio images. It can also generate
tones. The PWM uses 16-bit resolution and a 4 x 16 data FIFO to generate
sound.
• Legacy parallel interfaces
• Single/dual channel LVDS display interface
• Analog TV or VGA interfaces
• Image enhancement—color adjustment and gamut mapping, gamma
• Video/graphics combining
• Support for display backlight reduction
• Image conversion—resizing, rotation, inversion and color space
• Hardware de-interlacing support
• Synchronization and control capabilities, allowing autonomous
• Open drain design
• Glitch suppression circuit design
• Multiple keys detection
• Standby key press detection
• 1 clock pair
• 4 data pairs
correction and contrast enhancement
conversion
operation.
the standardize MediaLB protocol (up to 50 Mbps).
Brief Description
Freescale Semiconductor
®
data network, using