MCIMX53-START Freescale Semiconductor, MCIMX53-START Datasheet - Page 75

• Manufacturer Part Number: MCIMX53-START
• Description: KIT DEVELOPMENT I.MX53
• Manufacturer: Freescale Semiconductor
• Series: i.MX53r
• Type: MCUr

Specifications of MCIMX53-START

• Contents: Board
• Silicon Manufacturer: Freescale
• Core Architecture: ARM
• Core Sub-architecture: Cortex - A8
• Silicon Core Number: I.MX5
• Silicon Family Name: I.MX53
• Peak Reflow Compatible (260 C): Yes
• Rohs Compliant: Yes
• Leaded Process Compatible: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: i.MX53
• Lead Free Status / Rohs Status: Supplier Unconfirmed

4.7.5.2
The MII transmit signal timing affects the FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER, and
FEC_TX_CLK signals. The transmitter functions correctly up to a FEC_TX_CLK maximum frequency
of 25 MHz + 1%. There is no minimum frequency requirement. In addition, the processor clock frequency
must exceed twice the FEC_TX_CLK frequency.
Table 49
diagram for the values listed in
Freescale Semiconductor
1
2
FEC_TX_EN, FEC_TX_CLK, and FEC_TXD0 have the same timing in 10 Mbps 7-wire interface mode.
Test conditions: 25pF on each output signal.
Num
M5
M6
M7
M8
FEC_RXD[3:0] (inputs)
FEC_RX_CLK (input)
lists MII transmit channel timing parameters.
FEC_TX_CLK to FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER invalid
FEC_TX_CLK to FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER valid
FEC_TX_CLK pulse width high
FEC_TX_CLK pulse width low
MII Transmit Signal Timing
FEC_RX_ER
FEC_RX_DV
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1
Figure 36. MII Receive Signal Timing Diagram
Characteristic
Table
Table 49. MII Transmit Signal Timing
49.
M1
1 2
M2
M3
Figure 37
shows MII transmit signal timing
35%
35%
Min
—
M4
5
Max
65%
65%
—
20
Electrical Characteristics
FEC_TX_CLK period
FEC_TX_CLK period
Unit
ns
ns
75