MCIMX53-START Freescale Semiconductor, MCIMX53-START Datasheet - Page 65

• Manufacturer Part Number: MCIMX53-START
• Description: KIT DEVELOPMENT I.MX53
• Manufacturer: Freescale Semiconductor
• Series: i.MX53r
• Type: MCUr

Specifications of MCIMX53-START

• Contents: Board
• Silicon Manufacturer: Freescale
• Core Architecture: ARM
• Core Sub-architecture: Cortex - A8
• Silicon Core Number: I.MX5
• Silicon Family Name: I.MX53
• Peak Reflow Compatible (260 C): Yes
• Rohs Compliant: Yes
• Leaded Process Compatible: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: i.MX53
• Lead Free Status / Rohs Status: Supplier Unconfirmed

4.7.2.1
Figure 30
characteristics.
Freescale Semiconductor
RDY
SSx
SCLK
MOSI
MISO
1
2
See specific I/O AC parameters
SPI_RDY is sampled internally by ipg_clk and is asynchronous to all other CSPI signals.
CS10
CS1
CS2
CS3
CS4
CS5
CS6
CS7
CS8
CS9
ID
CS10
depicts the timing of CSPI in master mode.
CSPI Master Mode Timing
SCLK Cycle Time
SCLK High or Low Time
SCLK Rise or Fall
SSx pulse width
SSx Lead Time (Slave Select setup
time)
SSx Lag Time (SS hold time)
MOSI Propagation Delay
(C
MISO Setup Time
MISO Hold Time
RDY to SSx Time
CS8
LOAD
= 20 pF)
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1
Parameter
CS1
CS7
Figure 30. CSPI/ECSPI Master Mode Timing Diagram
CS9
2
1
Table 41. CSPI Master Mode Timing Parameters
Section 4.5, “I/O AC
CS3
CS3
Parameters”
t
RISE/FALL
Symbol
t
t
PDmosi
t
t
t
t
t
Smiso
Hmiso
SDRY
CSLH
t
HCS
t
SCS
SW
clk
Table 41
CS2
CS2
lists the CSPI master mode timing
Min
60
26
26
26
26
–1
—
5
5
5
CS6
Max
21
—
—
—
—
—
—
—
—
—
Electrical Characteristics
CS4
CS5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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