MCIMX53-START Freescale Semiconductor, MCIMX53-START Datasheet - Page 64

• Manufacturer Part Number: MCIMX53-START
• Description: KIT DEVELOPMENT I.MX53
• Manufacturer: Freescale Semiconductor
• Series: i.MX53r
• Type: MCUr

Specifications of MCIMX53-START

• Contents: Board
• Silicon Manufacturer: Freescale
• Core Architecture: ARM
• Core Sub-architecture: Cortex - A8
• Silicon Core Number: I.MX5
• Silicon Family Name: I.MX53
• Peak Reflow Compatible (260 C): Yes
• Rohs Compliant: Yes
• Leaded Process Compatible: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: i.MX53
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Electrical Characteristics
Figure 29
4.7
The following subsections provide information on external peripheral interfaces.
4.7.1
The AUDMUX provides a programmable interconnect logic for voice, audio and data routing between
internal serial interfaces (SSIs) and external serial interfaces (audio and voice codecs). The AC timing of
AUDMUX external pins is governed by the SSI module. For more information, see the respective SSI
electrical specifications found within this document.
4.7.2
This section describes the timing parameters of the CSPI and ECSPI blocks. The CSPI and ECSPI have
separate timing parameters for master and slave modes. The nomenclature used with the CSPI / ECSPI
modules and the respective routing of these signals is shown in
64
ECSPI-1
ECSPI-2
CSPI
DQS (input)
DQ (input)
SDCLK_B
SDCLK
External Peripheral Interfaces Parameters
Block Instance
shows the read timing parameters.
AUDMUX Timing Parameters
CSPI and ECSPI Timing Parameters
To receive the reported setup/hold values, write calibration should be
perform to locate the DQS in the middle of DQ window.
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1
Figure 29. DDR SDRAM DQ vs. DQS and SDCLK Read Cycle
DDR27
Table 40. CSPI Nomenclature and Routing
GPIO, KPP, DISP0_DAT, CSI0_DAT and EIM_D through IOMUXC
DISP0_DAT, CSI0_DAT and EIM through IOMUXC
DISP0_DAT, EIM_A/D, SD1 and SD2 through IOMUXC
DATA
DDR26
DATA
NOTE
DATA
DATA
Table
I/O Access
DATA
40.
DATA
Freescale Semiconductor
DATA
DATA