ATTINY84V-10PU Atmel, ATTINY84V-10PU Datasheet - Page 102
![no-image](/images/manufacturer_photos/0/0/78/atmel_sml.jpg)
ATTINY84V-10PU
Manufacturer Part Number
ATTINY84V-10PU
Description
AVR MCU, 8K FLASH, 512B RAM, 512B EE
Manufacturer
Atmel
Datasheet
1.ATTINY84V-10PU.pdf
(233 pages)
Specifications of ATTINY84V-10PU
Controller Family/series
AVR Tiny
No. Of I/o's
12
Eeprom Memory Size
512Byte
Ram Memory Size
1KB
Cpu Speed
10MHz
Core Size
8bit
Program Memory Size
8KB
Oscillator Type
External, Internal
Processor Series
ATTINY8x
Core
AVR8
Data Bus Width
8 bit
Program Memory Type
Flash
Data Ram Size
512 B
Interface Type
SPI
Maximum Clock Frequency
10 MHz
Number Of Programmable I/os
12
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
Package / Case
PDIP-14
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATTINY84V-10PU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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14.8
102
Compare Match Output Unit
ATtiny24/44/84
The Compare Output mode (COM1x1:0) bits have two functions. The Waveform Generator uses
the COM1x1:0 bits for defining the Output Compare (OC1x) state at the next compare match.
Secondly the COM1x1:0 bits control the OC1x pin output source.
shows a simplified schematic of the logic affected by the COM1x1:0 bit setting. The I/O Regis-
ters, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of the general I/O port
control registers (DDR and PORT) that are affected by the COM1x1:0 bits are shown. When
referring to the OC1x state, the reference is for the internal OC1x Register, not the OC1x pin. If
a system reset occur, the OC1x Register is reset to “0”.
Figure 14-5. Compare Match Output Unit, Schematic
The general I/O port function is overridden by the Output Compare (OC1x) from the Waveform
Generator if either of the COM1x1:0 bits are set. However, the OC1x pin direction (input or out-
put) is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction
Register bit for the OC1x pin (DDR_OC1x) must be set as output before the OC1x value is visi-
ble on the pin. The port override function is generally independent of the Waveform Generation
mode, but there are some exceptions. See
and
The design of the Output Compare pin logic allows initialization of the OC1x state before the out-
put is enabled. Note that some COM1x1:0 bit settings are reserved for certain modes of
operation. See
The COM1x1:0 bits have no effect on the Input Capture unit.
Table 14-3 on page 114
COMnx1
COMnx0
FOCnx
clk
I/O
”Register Description” on page 113
Waveform
Generator
for details.
D
D
D
PORT
OCnx
DDR
Table 14-1 on page
Q
Q
Q
1
0
113,
Figure 14-5 on page 102
Table 14-2 on page 113
8006F–AVR–02/07
OCnx
Pin
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