ATTINY84V-10PU Atmel, ATTINY84V-10PU Datasheet - Page 127

• Manufacturer Part Number: ATTINY84V-10PU
• Description: AVR MCU, 8K FLASH, 512B RAM, 512B EE
• Manufacturer: Atmel

Specifications of ATTINY84V-10PU

• Controller Family/series: AVR Tiny
• No. Of I/o's: 12
• Eeprom Memory Size: 512Byte
• Ram Memory Size: 1KB
• Cpu Speed: 10MHz
• Core Size: 8bit
• Program Memory Size: 8KB
• Oscillator Type: External, Internal
• Processor Series: ATTINY8x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Data Ram Size: 512 B
• Interface Type: SPI
• Maximum Clock Frequency: 10 MHz
• Number Of Programmable I/os: 12
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Package / Case: PDIP-14
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

16.3.4
8006F–AVR–02/07
Two-wire Mode
The USI Two-wire mode is compliant to the Inter IC (TWI) bus protocol, but without slew rate lim-
iting on outputs and input noise filtering. Pin names used by this mode are SCL and SDA.
Figure 16-4. Two-wire Mode Operation, Simplified Diagram
Figure 16-4 on page 127
one as Slave. It is only the physical layer that is shown since the system operation is highly
dependent of the communication scheme used. The main differences between the Master and
Slave operation at this level, is the serial clock generation which is always done by the Master,
and only the Slave uses the clock control unit. Clock generation must be implemented in soft-
ware, but the shift operation is done automatically by both devices. Note that only clocking on
negative edge for shifting data is of practical use in this mode. The slave can insert wait states at
start or end of transfer by forcing the SCL clock low. This means that the Master must always
check if the SCL line was actually released after it has generated a positive edge.
Since the clock also increments the counter, a counter overflow can be used to indicate that the
transfer is completed. The clock is generated by the master by toggling the USCK pin via the
PORT Register.
The data direction is not given by the physical layer. A protocol, like the one used by the TWI-
bus, must be implemented to control the data flow.
SLAVE
MASTER
Bit7
Bit7
Bit6
Bit6
Bit5
Bit5
shows two USI units operating in Two-wire mode, one as Master and
Bit4
Bit4
Bit3
Bit3
Bit2
Bit2
Bit1
Bit1
Bit0
Bit0
Two-wire Clock
Control Unit
PORTxn
HOLD
SCL
ATtiny24/44/84
SDA
SCL
SDA
SCL
VCC
127