ATTINY84V-10PU Atmel, ATTINY84V-10PU Datasheet - Page 170

• Manufacturer Part Number: ATTINY84V-10PU
• Description: AVR MCU, 8K FLASH, 512B RAM, 512B EE
• Manufacturer: Atmel

Specifications of ATTINY84V-10PU

• Controller Family/series: AVR Tiny
• No. Of I/o's: 12
• Eeprom Memory Size: 512Byte
• Ram Memory Size: 1KB
• Cpu Speed: 10MHz
• Core Size: 8bit
• Program Memory Size: 8KB
• Oscillator Type: External, Internal
• Processor Series: ATTINY8x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Data Ram Size: 512 B
• Interface Type: SPI
• Maximum Clock Frequency: 10 MHz
• Number Of Programmable I/os: 12
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Package / Case: PDIP-14
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

21.6.2
Table 21-11. Serial Programming Instruction Set
170
Instruction/Operation
Programming Enable
Chip Erase (Program Memory/EEPROM)
Poll RDY/BSY
Load Instructions
Load Extended Address byte
Load Program Memory Page, High byte
Load Program Memory Page, Low byte
Load EEPROM Memory Page (page access)
Read Instructions
Read Program Memory, High byte
Read Program Memory, Low byte
Read EEPROM Memory
Read Lock bits
Read Signature Byte
Read Fuse bits
Read Fuse High bits
Read Extended Fuse Bits
Read Calibration Byte
Write Instructions
Write Program Memory Page
Write EEPROM Memory
Write EEPROM Memory Page (page access)
Write Lock bits
ATtiny24/44/84
Serial Programming Instruction set
(6)
(1)
Table 21-10. Minimum Wait Delay Before Writing the Next Flash or EEPROM Location
Table 21-11 on page 170
Symbol
t
t
t
t
WD_FLASH
WD_EEPROM
WD_ERASE
WD_FUSE
Byte 1
$AC
$AC
$4D
$C1
$4C
$C0
$C2
$AC
$F0
$A0
$58
$50
$38
$48
$40
$28
$20
$30
$50
$58
and
Figure 21-2 on page 171
adr MSB
adr MSB
adr MSB
adr MSB
adr MSB
Byte 2
$E0
$53
$80
$00
$00
$00
$00
$00
$00
$00
$08
$08
$00
$00
$00
Instruction Format
Minimum Wait Delay
describes the Instruction set.
Extended adr
4.5 ms
4.0 ms
4.0 ms
4.5 ms
adr LSB
adr LSB
adr LSB
adr LSB
adr LSB
adr LSB
adr LSB
adr LSB
adr LSB
adr LSB
Byte 3
$00
$00
$00
$00
$00
$00
$00
$00
$00
high data byte out
low data byte out
high data byte in
low data byte in
data byte out
data byte out
data byte out
data byte out
data byte out
data byte out
data byte out
data byte out
data byte in
data byte in
data byte in
8006F–AVR–02/07
Byte4
$00
$00
$00
$00
$00