ATTINY84V-10PU Atmel, ATTINY84V-10PU Datasheet - Page 82

• Manufacturer Part Number: ATTINY84V-10PU
• Description: AVR MCU, 8K FLASH, 512B RAM, 512B EE
• Manufacturer: Atmel

Specifications of ATTINY84V-10PU

• Controller Family/series: AVR Tiny
• No. Of I/o's: 12
• Eeprom Memory Size: 512Byte
• Ram Memory Size: 1KB
• Cpu Speed: 10MHz
• Core Size: 8bit
• Program Memory Size: 8KB
• Oscillator Type: External, Internal
• Processor Series: ATTINY8x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Data Ram Size: 512 B
• Interface Type: SPI
• Maximum Clock Frequency: 10 MHz
• Number Of Programmable I/os: 12
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Package / Case: PDIP-14
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

13.8
82
Timer/Counter Timing Diagrams
ATtiny24/44/84
one allows the OC0A pin to toggle on Compare Matches if the WGM02 bit is set. This option is
not available for the OC0B pin (See
visible on the port pin if the data direction for the port pin is set as output. The PWM waveform is
generated by clearing (or setting) the OC0x Register at the Compare Match between OCR0x
and TCNT0 when the counter increments, and setting (or clearing) the OC0x Register at Com-
pare Match between OCR0x and TCNT0 when the counter decrements. The PWM frequency for
the output when using phase correct PWM can be calculated by the following equation:
The N variable represents the prescale factor (1, 8, 64, 256, or 1024).
The extreme values for the OCR0A Register represent special cases when generating a PWM
waveform output in the phase correct PWM mode. If the OCR0A is set equal to BOTTOM, the
output will be continuously low and if set equal to MAX the output will be continuously high for
non-inverted PWM mode. For inverted PWM the output will have the opposite logic values.
At the very start of period 2 in
even though there is no Compare Match. The point of this transition is to guaratee symmetry
around BOTTOM. There are two cases that give a transition without Compare Match.
• OCR0A changes its value from MAX, like in
• The timer starts counting from a value higher than the one in OCR0A, and for that reason
The Timer/Counter is a synchronous design and the timer clock (clk
clock enable signal in the following figures. The figures include information on when Interrupt
Flags are set.
The figure shows the count sequence close to the MAX value in all modes other than phase cor-
rect PWM mode.
Figure 13-8. Timer/Counter Timing Diagram, no Prescaling
Figure 13-9 on page 83
is MAX the OCn pin value is the same as the result of a down-counting Compare Match. To
ensure symmetry around BOTTOM the OCn value at MAX must correspond to the result of an
up-counting Compare Match.
misses the Compare Match and hence the OCn change that would have happened on the way
up.
TCNTn
(clk
TOVn
clk
clk
I/O
I/O
Tn
/1)
Figure 13-8 on page 82
shows the same timing data, but with the prescaler enabled.
MAX - 1
Figure 13-7 on page 81
f
Table 13-4 on page
OCnxPCPWM
contains timing data for basic Timer/Counter operation.
MAX
Figure 13-7 on page
=
----------------- -
N 510
f
clk_I/O
⋅
85). The actual OC0x value will only be
OCn has a transition from high to low
BOTTOM
81. When the OCR0A value
T0
) is therefore shown as a
BOTTOM + 1
8006F–AVR–02/07