ATTINY84V-10PU Atmel, ATTINY84V-10PU Datasheet - Page 126
![no-image](/images/manufacturer_photos/0/0/78/atmel_sml.jpg)
ATTINY84V-10PU
Manufacturer Part Number
ATTINY84V-10PU
Description
AVR MCU, 8K FLASH, 512B RAM, 512B EE
Manufacturer
Atmel
Datasheet
1.ATTINY84V-10PU.pdf
(233 pages)
Specifications of ATTINY84V-10PU
Controller Family/series
AVR Tiny
No. Of I/o's
12
Eeprom Memory Size
512Byte
Ram Memory Size
1KB
Cpu Speed
10MHz
Core Size
8bit
Program Memory Size
8KB
Oscillator Type
External, Internal
Processor Series
ATTINY8x
Core
AVR8
Data Bus Width
8 bit
Program Memory Type
Flash
Data Ram Size
512 B
Interface Type
SPI
Maximum Clock Frequency
10 MHz
Number Of Programmable I/os
12
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
Package / Case
PDIP-14
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATTINY84V-10PU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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16.3.3
126
ATtiny24/44/84
SPI Slave Operation Example
The following code demonstrates how to use the USI module as a SPI Slave:
The code is size optimized using only eight instructions (+ ret). The code example assumes that
the DO is configured as output and USCK pin is configured as input in the DDR Register. The
value stored in register r16 prior to the function is called is transferred to the master device, and
when the transfer is completed the data received from the Master is stored back into the r16
Register.
Note that the first two instructions is for initialization only and needs only to be executed
once.These instructions sets Three-wire mode and positive edge Shift Register clock. The loop
is repeated until the USI Counter Overflow Flag is set.
ret
init:
...
SlaveSPITransfer:
SlaveSPITransfer_loop:
out
in
ldi
out
out
ldi
out
in
sbrs
rjmp
in
ret
USICR,r17
r16,USIDR
r16,(1<<USIWM0)|(1<<USICS1)
USICR,r16
USIDR,r16
r16,(1<<USIOIF)
USISR,r16
r16, USISR
r16, USIOIF
SlaveSPITransfer_loop
r16,USIDR
8006F–AVR–02/07
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