ATTINY84V-10PU Atmel, ATTINY84V-10PU Datasheet - Page 113
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ATTINY84V-10PU
Manufacturer Part Number
ATTINY84V-10PU
Description
AVR MCU, 8K FLASH, 512B RAM, 512B EE
Manufacturer
Atmel
Datasheet
1.ATTINY84V-10PU.pdf
(233 pages)
Specifications of ATTINY84V-10PU
Controller Family/series
AVR Tiny
No. Of I/o's
12
Eeprom Memory Size
512Byte
Ram Memory Size
1KB
Cpu Speed
10MHz
Core Size
8bit
Program Memory Size
8KB
Oscillator Type
External, Internal
Processor Series
ATTINY8x
Core
AVR8
Data Bus Width
8 bit
Program Memory Type
Flash
Data Ram Size
512 B
Interface Type
SPI
Maximum Clock Frequency
10 MHz
Number Of Programmable I/os
12
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
Package / Case
PDIP-14
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATTINY84V-10PU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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14.11 Register Description
14.11.1
8006F–AVR–02/07
TCCR1A – Timer/Counter1 Control Register A
• Bit 7:6 – COM1A1:0: Compare Output Mode for Channel A
• Bit 5:4 – COM1B1:0: Compare Output Mode for Channel B
The COM1A1:0 and COM1B1:0 control the Output Compare pins (OC1A and OC1B respec-
tively) behavior. If one or both of the COM1A1:0 bits are written to one, the OC1A output
overrides the normal port functionality of the I/O pin it is connected to. If one or both of the
COM1B1:0 bit are written to one, the OC1B output overrides the normal port functionality of the
I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit correspond-
ing to the OC1A or OC1B pin must be set in order to enable the output driver.
When the OC1A or OC1B is connected to the pin, the function of the COM1x1:0 bits is depen-
dent of the WGM13:0 bits setting.
when the WGM13:0 bits are set to a Normal or a CTC mode (non-PWM).
Table 14-1.
Table 14-2 on page 113
the fast PWM mode.
Table 14-2.
Note:
Bit
0x2F (0x4F)
Read/Write
Initial Value
COM1A1/COM1B1
COM1A1/COM1B1
1. A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set. In
0
0
1
1
0
0
1
1
this case the compare match is ignored, but the set or clear is done at BOTTOM.
Mode” on page 104
COM1A1
Compare Output Mode, non-PWM
Compare Output Mode, Fast PWM
R/W
7
0
COM1A0
shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to
COM1A0/COM1B0
COM1A0/COM1B0
R/W
6
0
for more details.
0
1
0
1
0
1
0
1
COM1B1
Table 14-1 on page 113
R/W
5
0
COM1B0
R/W
4
0
Normal port operation, OC1A/OC1B disconnected.
Toggle OC1A/OC1B on Compare Match.
Clear OC1A/OC1B on Compare Match (Set output to
low level).
Set OC1A/OC1B on Compare Match (Set output to
high level).
Normal port operation, OC1A/OC1B disconnected.
WGM13=0: Normal port operation, OC1A/OC1B
disconnected.
WGM13=1: Toggle OC1A on Compare Match, OC1B
reserved.
Clear OC1A/OC1B on Compare Match, set
OC1A/OC1B at BOTTOM (non-inverting mode)
Set OC1A/OC1B on Compare Match, clear
OC1A/OC1B at BOTTOM (inverting mode)
Description
Description
(1)
R
3
–
0
shows the COM1x1:0 bit functionality
R
2
–
0
ATtiny24/44/84
WGM11
R/W
1
0
WGM10
R/W
0
0
”Fast PWM
TCCR1A
113
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