ATTINY84V-10PU Atmel, ATTINY84V-10PU Datasheet - Page 24

• Manufacturer Part Number: ATTINY84V-10PU
• Description: AVR MCU, 8K FLASH, 512B RAM, 512B EE
• Manufacturer: Atmel

Specifications of ATTINY84V-10PU

• Controller Family/series: AVR Tiny
• No. Of I/o's: 12
• Eeprom Memory Size: 512Byte
• Ram Memory Size: 1KB
• Cpu Speed: 10MHz
• Core Size: 8bit
• Program Memory Size: 8KB
• Oscillator Type: External, Internal
• Processor Series: ATTINY8x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Data Ram Size: 512 B
• Interface Type: SPI
• Maximum Clock Frequency: 10 MHz
• Number Of Programmable I/os: 12
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Package / Case: PDIP-14
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

24
ATtiny24/44/84
• Bit 7 – Res: Reserved Bit
This bit is reserved for future use and will always read as 0 in ATtiny24/44/84. For compatibility
with future AVR devices, always write this bit to zero. After reading, mask out this bit.
• Bit 6 – Res: Reserved Bit
This bit is reserved in the ATtiny24/44/84 and will always read as zero.
• Bits 5, 4 – EEPM1 and EEPM0: EEPROM
Mode Bits
The EEPROM Programming mode bits setting defines which programming action that will be
triggered when writing EEPE. It is possible to program data in one atomic operation (erase the
old value and program the new value) or to split the Erase and Write operations in two different
operations. The Programming times for the different modes are shown in
is set, any write to EEPMn will be ignored. During reset, the EEPMn bits will be reset to 0b00
unless the EEPROM is busy programming.
Table 6-1.
• Bit 3 – EERIE: EEPROM Ready Interrupt Enable
Writing EERIE to one enables the EEPROM Ready Interrupt if the I-bit in SREG is set. Writing
EERIE to zero disables the interrupt. The EEPROM Ready Interrupt generates a constant inter-
rupt when Non-volatile memory is ready for programming.
• Bit 2 – EEMPE: EEPROM Master Program Enable
The EEMPE bit determines whether writing EEPE to one will have effect or not.
When EEMPE is set, setting EEPE within four clock cycles will program the EEPROM at the
selected address. If EEMPE is zero, setting EEPE will have no effect. When EEMPE has been
written to one by software, hardware clears the bit to zero after four clock cycles.
• Bit 1 – EEPE: EEPROM Program Enable
The EEPROM Program Enable Signal EEPE is the programming enable signal to the EEPROM.
When EEPE is written, the EEPROM will be programmed according to the EEPMn bits setting.
The EEMPE bit must be written to one before a logical one is written to EEPE, otherwise no
EEPROM write takes place. When the write access time has elapsed, the EEPE bit is cleared
by hardware. When EEPE has been set, the CPU is halted for two cycles before the next
instruction is executed.
• Bit 0 – EERE: EEPROM Read Enable
The EEPROM Read Enable Signal – EERE – is the read strobe to the EEPROM. When the cor-
rect address is set up in the EEAR Register, the EERE bit must be written to one to trigger the
EEPM1
0
0
1
1
EEPM0
EEPROM Mode Bits
0
1
0
1
Programming
3.4 ms
1.8 ms
1.8 ms
Time
–
Operation
Erase and Write in one operation (Atomic Operation)
Erase Only
Write Only
Reserved for future use
Table
6-1. While EEPE
8006F–AVR–02/07