ATTINY84V-10PU Atmel, ATTINY84V-10PU Datasheet - Page 116
ATTINY84V-10PU
Manufacturer Part Number
ATTINY84V-10PU
Description
AVR MCU, 8K FLASH, 512B RAM, 512B EE
Manufacturer
Atmel
Datasheet
1.ATTINY84V-10PU.pdf
(233 pages)
Specifications of ATTINY84V-10PU
Controller Family/series
AVR Tiny
No. Of I/o's
12
Eeprom Memory Size
512Byte
Ram Memory Size
1KB
Cpu Speed
10MHz
Core Size
8bit
Program Memory Size
8KB
Oscillator Type
External, Internal
Processor Series
ATTINY8x
Core
AVR8
Data Bus Width
8 bit
Program Memory Type
Flash
Data Ram Size
512 B
Interface Type
SPI
Maximum Clock Frequency
10 MHz
Number Of Programmable I/os
12
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
Package / Case
PDIP-14
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATTINY84V-10PU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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14.11.3
116
ATtiny24/44/84
TCCR1C – Timer/Counter1 Control Register C
When the ICR1 is used as TOP value (see description of the WGM13:0 bits located in the
TCCR1A and the TCCR1B Register), the ICP1 is disconnected and consequently the Input Cap-
ture function is disabled.
• Bit 5 – Reserved Bit
This bit is reserved for future use. For ensuring compatibility with future devices, this bit must be
written to zero when TCCR1B is written.
• Bit 4:3 – WGM13:2: Waveform Generation Mode
See TCCR1A Register description.
• Bit 2:0 – CS12:0: Clock Select
The three Clock Select bits select the clock source to be used by the Timer/Counter, see
14-10
Table 14-5.
If external pin modes are used for the Timer/Counter1, transitions on the T1 pin will clock the
counter even if the pin is configured as an output. This feature allows software control of the
counting.
• Bit 7 – FOC1A: Force Output Compare for Channel A
• Bit 6 – FOC1B: Force Output Compare for Channel B
The FOC1A/FOC1B bits are only active when the WGM13:0 bits specifies a non-PWM mode.
However, for ensuring compatibility with future devices, these bits must be set to zero when
TCCR1A is written when operating in a PWM mode. When writing a logical one to the
FOC1A/FOC1B bit, an immediate compare match is forced on the Waveform Generation unit.
The OC1A/OC1B output is changed according to its COM1x1:0 bits setting. Note that the
FOC1A/FOC1B bits are implemented as strobes. Therefore it is the value present in the
COM1x1:0 bits that determine the effect of the forced compare.
Bit
0x22 (0x42)
Read/Write
Initial Value
CS12
0
0
0
0
1
1
1
1
and
Figure
CS11
0
0
1
1
0
0
1
1
Clock Select Bit Description
FOC1A
W
7
0
14-11.
CS10
FOC1B
0
1
0
1
0
1
0
1
W
6
0
Description
No clock source (Timer/Counter stopped).
clk
clk
clk
clk
clk
External clock source on T1 pin. Clock on falling edge.
External clock source on T1 pin. Clock on rising edge.
I/O
I/O
I/O
I/O
I/O
R
5
–
0
/1 (No prescaling)
/8 (From prescaler)
/64 (From prescaler)
/256 (From prescaler)
/1024 (From prescaler)
R
4
–
0
R
3
–
0
R
2
–
0
–
R
1
0
R
0
–
0
8006F–AVR–02/07
TCCR1C
Figure
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