ATTINY84V-10PU Atmel, ATTINY84V-10PU Datasheet - Page 163
ATTINY84V-10PU
Manufacturer Part Number
ATTINY84V-10PU
Description
AVR MCU, 8K FLASH, 512B RAM, 512B EE
Manufacturer
Atmel
Datasheet
1.ATTINY84V-10PU.pdf
(233 pages)
Specifications of ATTINY84V-10PU
Controller Family/series
AVR Tiny
No. Of I/o's
12
Eeprom Memory Size
512Byte
Ram Memory Size
1KB
Cpu Speed
10MHz
Core Size
8bit
Program Memory Size
8KB
Oscillator Type
External, Internal
Processor Series
ATTINY8x
Core
AVR8
Data Bus Width
8 bit
Program Memory Type
Flash
Data Ram Size
512 B
Interface Type
SPI
Maximum Clock Frequency
10 MHz
Number Of Programmable I/os
12
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
Package / Case
PDIP-14
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATTINY84V-10PU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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ATtiny24/44/84
will auto-clear upon completion of a Page Write, or if no SPM instruction is executed within four
clock cycles. The CPU is halted during the entire Page Write operation.
• Bit 1 – PGERS: Page Erase
If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock
cycles executes Page Erase. The page address is taken from the high part of the Z-pointer. The
data in R1 and R0 are ignored. The PGERS bit will auto-clear upon completion of a Page Erase,
or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire
Page Write operation.
• Bit 0 – SPMEN: Store Program Memory Enable
This bit enables the SPM instruction for the next four clock cycles. If written to one together with
either CTPB, RFLB, PGWRT, or PGERS, the following SPM instruction will have a special
meaning, see description above. If only SPMEN is written, the following SPM instruction will
store the value in R1:R0 in the temporary page buffer addressed by the Z-pointer. The LSB of
the Z-pointer is ignored. The SPMEN bit will auto-clear upon completion of an SPM instruction,
or if no SPM instruction is executed within four clock cycles. During Page Erase and Page Write,
the SPMEN bit remains high until the operation is completed.
Writing any other combination than “10001”, “01001”, “00101”, “00011” or “00001” in the lower
five bits will have no effect.
163
8006F–AVR–02/07
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