CY7C65113C-SXCT Cypress Semiconductor Corp, CY7C65113C-SXCT Datasheet
CY7C65113C-SXCT
Specifications of CY7C65113C-SXCT
Related parts for CY7C65113C-SXCT
CY7C65113C-SXCT Summary of contents
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... Operating voltage from 4.0V to 5.5V DC ■ Operating temperature from 0 to 70 C ■ Available in 28-pin SOIC (-SXC) package ■ Industry-standard programmer support ■ • 198 Champion Court • San Jose CY7C65113C , CA 95134-1709 • 408-943-2600 Revised March 31, 2011 [+] Feedback ...
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... The SIE allows the USB host to communicate with the hub and functions integrated into the microcontroller. The CY7C65113C part includes a 1:4 hub repeater with one upstream port and four downstream ports. The USB Hub allows power management control of the downstream ports by using GPIO pins assigned by the user firmware ...
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... P0[0] GPIO PORT 0 P0[7] P1[0] GPIO PORT 1 P1[ comp. SCLK SDATA Interface 2 *I C-compatible interface enabled by firmware through P1[1:0] CY7C65113C D+[0] Upstream USB Port D–[0] Downstream USB Ports USB D+[1] D–[1] Transceiver USB D+[2] Transceiver D–[2] USB D+[3] Transceiver D–[3] USB ...
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... Document #: 38-08002 Rev. *F Sample Schematic .......................................................... 41 Absolute Maximum Ratings .......................................... 41 Electrical Characteristics ............................................... 42 Switching Characteristics .............................................. 43 Ordering Information ...................................................... 44 Ordering Code Definitions ......................................... 44 Package Diagram ............................................................ 45 Acronyms ........................................................................ 46 Document Conventions ................................................. 46 Units of Measure ....................................................... 46 Document History Page ................................................. 47 Sales, Solutions, and Legal Information ...................... 48 Worldwide Sales and Design Support ....................... 48 Products .................................................................... 48 PSoC Solutions ......................................................... 48 CY7C65113C Page [+] Feedback ...
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... D+[4], D–[4] I/O 21 I/O P1[7:0] 11, 15, 12, 16, 13, 17, 14 I/O P1[2:0] 25, 27, 26 XTAL XTAL OUT 1 OUT GND REF Document #: 38-08002 Rev. *F Figure 1. CY7C65113C 28-Pin SOIC Top View XTALOUT P1[1] XTALIN 3 26 P1[0] V REF 4 P1[2] GND 25 D–[3] D+[ D+[3] D–[ D–[4] D+[ D+[4] D– ...
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... USB Address B, Endpoint 0 Counter R/W USB Address B, Endpoint 0 Configuration, or USB Address A, Endpoint 3 in 5-endpoint mode R/W USB Address B, Endpoint 1 Counter R/W USB Address B, Endpoint 1 Configuration, or USB Address A, Endpoint 4 in 5-endpoint mode R/W Hub Downstream Port Connect Status R/W Hub Downstream Ports Enable CY7C65113C Page ...
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... PUSH X 7 SWAP A,X 4 SWAP A,DSP 6 MOV [expr],A 7 MOV [X+expr], [expr], [X+expr],A 7 AND [expr],A 5 AND [X+expr],A 7 XOR [expr],A 8 XOR [X+expr],A 4 IOWX [X+expr] 5 CPL 6 ASL CY7C65113C Page operand opcode cycles 20 4 acc direct 23 7 index 24 8 acc ...
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... Programming Model 14-bit Program Counter The 14-bit Program Counter (PC) allows access PROM available with the CY7C65113C architecture. The top 32 bytes of the ROM in the 8K part are reserved for testing purposes. The program counter is cleared during reset, such that the first instruction executed after a reset is at address 0x0000h. ...
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... USB address A endpoint 2 interrupt vector 0x000E USB address B endpoint 0 interrupt vector 0x0010 USB address B endpoint 1 interrupt vector 0x0012 Hub interrupt vector 0x0014 Reserved 0x0016 GPIO interrupt vector 2 0x0018 I C interrupt vector 0x001A Program Memory begins here 0x1FDF (8 KB -32) PROM ends here (CY7C65113C) CY7C65113C Page [+] Feedback ...
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... PSP by two. Data Memory Organization The CY7C65113C microcontrollers provide 256 bytes of data RAM. Normally, the SRAM is partitioned into four areas: program stack, user variables, data stack, and USB endpoint FIFOs. The following is one example of where the program stack, data stack, and user variables areas could be located ...
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... EQU 10h • MOV X, 3 • MOV A, [X+array]. This would have the effect of loading A with the fourth element of the SRAM “array” that begins at address 0x10. The fourth element would be at address 0x13. To Internal PLL CY7C65113C Page [+] Feedback ...
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... XTALIN with an oscillator does not work because the internal clock is effectively shorted to ground. Reset The CY7C65113C supports two resets: POR and WDR. Each of these resets causes: • all registers to be restored to their default states • the USB device addresses to be set to 0 • ...
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... Register). Document #: 38-08002 Rev. *F Suspend Mode The CY7C65113C can be placed into a low-power state by setting the Suspend bit of the Processor Status and Control register. All logic blocks in the device are turned off except the GPIO interrupt logic and the USB receiver. The clock oscillator and PLL, as well as the free-running and Watchdog timers, are shut down ...
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... Specifications ‘1’ is written to the unused data bit and the port is configured with open drain outputs, the unused data bit remains in an indeterminate state. Therefore unused port bit is programmed in open-drain mode, it must be written with a ‘0.’ CY7C65113C GPIO PIN sink Address 0x00 ...
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... As shown in this table below, when a GPIO port is configured with CMOS outputs, interrupts from that port are disabled. During reset, all of the bits in the GPIO Configuration Register are written with ‘0’ to select Hi-Z mode for all GPIO ports as the default configuration. CY7C65113C (Figure ) and (Figure 10 through ...
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... P0.5 Intr P0.4 Intr P0.3 Intr Enable Enable Enable Figure 10. Port 1 Interrupt Enable Reserved Reserved Reserved - - - - - - CY7C65113C Interrupt Polarity 0 Disabled 1 – (Falling Edge) 0 Disabled 1 Disabled 0 Disabled 1 – (Falling Edge) 0 Disabled 1 + (Rising Edge) Address 0x04 P0.2 Intr P0.1 Intr P0.0 Intr Enable ...
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... Timer Bit 4 Timer Bit Figure 12. Timer MSB Register Reserved Reserved Timer Bit 11 Timer Bit 10 – – Figure 13. Timer Block Diagram CY7C65113C Address 0x24 Timer Bit 2 Timer Bit 1 Timer Bit Address 0x25 Timer Bit 9 Timer Bit 1.024-ms interrupt 128- s interrupt 1 MHz clock ...
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... C-compatible interface is the same as that of GPIO port 1. Note 2 that the I (max All control of the I performed by the Status and 2 Figure 15 Data Register Data Data Data 3 R/W R/W R CY7C65113C 2 C-compatible function is Address 0x09 Reserved I C Port Reserved Width R/W R/W R Position P1[1:0], 0:SCL, 1:SDA 2 C interrupt Port Configuration 2 C-compatible functionality is 2 ...
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... This bit is set by firmware to enter transmit mode and per- form a data transmit in master or slave mode. Clearing this bit sets the part in receive mode. Firmware generally de- termines the value of this bit from the R/W bit associated with the I ignored when initially writing the MSTR Mode or the Re- CY7C65113C Address 0x28 ...
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... The USB Bus Reset Interrupt bit is set when the USB Bus Reset is detected on receiving a USB Bus Reset signal on the upstream port. The USB Bus Reset signal is a sin- gle-ended zero (SE0) that lasts from s. An SE0 CY7C65113C target address for the restart must ...
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... Enable Interrupt on I2C related activity Disable I2C related activity interrupt. (Refer to section .) Bit 7: Reserved Reserved EPB1 EPB0 Interrupt Interrupt Enable Enable – R/W R/W – CY7C65113C Address 0X20 1.024-ms 128-s USB Bus Interrupt Interrupt RST Enable Enable Interrupt Enable R/W R/W R/W 0 ...
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... ISR, instead of waiting for the RETI that exits the ISR. While the global interrupt enable bit is cleared, the presence of a pending interrupt can be detected by examining the IRQ Sense bit (Bit 7 in the Processor Status and Control Register). CY7C65113C Page [+] Feedback ...
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... USB Address B Endpoint 0 interrupt 0x0010 USB Address B Endpoint 1 interrupt 0x0012 USB Hub interrupt 0x0014 DAC interrupt 0x0016 GPIO interrupt 2 0x0018 I C interrupt CY7C65113C To CPU CPU IRQ Sense IRQ Global Int Enable Interrupt Sense Enable Bit Controlled by DI, EI, and CLR RETI Instructions ...
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... GPIO port as part of the GPIO configuration. All of the GPIO pins share a single interrupt vector, which means the firmware needs to read the GPIO ports with enabled interrupts to determine which pin or pins caused an interrupt. A block diagram of the GPIO interrupt logic is shown in Figure . CY7C65113C Page [+] Feedback ...
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... Status and Control Register that sets the Continue/Busy bit, without checking the value of the Continue/Busy bit. The Busy bit may otherwise be active and I register contents may be changed by the hardware during the transaction, until the I CY7C65113C Interrupt IRQout Priority Interrupt ...
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... USB host can read hub connection status to determine which (if any) of the downstream ports need to be enumerated. The following is a brief summary of the typical enumeration process of the CY7C65113C by the USB host. For a detailed description of the enumeration process, refer to the USB specification. ...
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... Figure 24. Hub Ports Enable Register Reserved Reserved Port 4 Enable Port 3 Enable Port 2 Enable Port 1 Enable R/W R/W R CY7C65113C Address 0x48 Port 3 Port 2 Port 1 Connect Connect Connect Status Status Status R/W ...
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... Figure 26. Hub Ports Force Low Register Force Low Force Low Force Low D+[3] D–[3] D+[2] R/W R/W R CY7C65113C below. The Hub Downstream Ports Control may cause current REF Address 0x4B Port 2 Port 1 Port 1 Control Bit 0 Control Bit 1 Control Bit 0 R/W R/W ...
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... A resume bit is set automatically when hardware detects a resume condition on a selectively suspended downstream port. The resume condition is a differential ‘1’ for a low-speed device and a differential ‘0’ for a full-speed device. These registers are cleared on reset or USB bus reset. CY7C65113C Address 0x4F ...
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... If Device Remote Wake-up is set, automatic hardware assertions take place on Resume events. USB Upstream Port Status and Control USB status and control is regulated by the USB Status and Control Register, as shown in cleared during reset. CY7C65113C Address 0x4D Port 3 Port 2 ...
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... Specification, Section 11.2.2 as well as USB 2.0 specification (section 11.2.5, page 304). USB Serial Interface Engine Operation The CY7C65113C SIE supports operation as a single device or a compound device. This section describes the two device addresses, the configurable endpoints, and the endpoint function ...
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... Document #: 38-08002 Rev. *F USB Device Endpoints The CY7C65113C controller supports up to two addresses and five endpoints for communication with the host. The configu- ration of these endpoints, and associated FIFOs, is controlled by bits [7,6] of the USB Status and Control Register controls the size of the endpoints and bit 6 controls the number of addresses ...
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... The format of these registers is shown in Figure 35. Figure 35. USB Endpoint Counter Registers Byte Count Byte Count Byte Count Bit 5 Bit 4 Bit 3 R/W R/W R CY7C65113C Table 10 for the appropriate endpoint zero Table 11. Table 12 Addresses 0x14, 0x16, 0x44 Mode Bit 2 Mode Bit 1 Mode Bit 0 R/W R/W R ...
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... For details on what conditions are required to generate an endpoint interrupt, refer to 4. The contents of the updated endpoint 0 mode and counter registers are locked, except the SETUP bit of the endpoint 0 mode register which was locked earlier. CY7C65113C Table 12. Page [+] Feedback ...
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... OUT token. The firmware needs to update the mode for the SIE to respond appropriately. See details on what modes will be changed by the SIE. A disabled endpoint will remain disabled until changed by firmware, and all CY7C65113C Comments 11, the SIE will change the endpoint Mode Bits Table 11 ...
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... USB request). This read will of course unlock the register. So care must be taken not to overwrite the register elsewhere. CY7C65113C Interrupt In Out ACK ...
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... updates updates updates 1 updates CY7C65113C ACK Mode Bits Response Intr ACK yes UC NoChange ignore yes UC NoChange ignore yes ACK Mode Bits Response Intr UC NoChange ignore no UC NoChange NAK yes UC NoChange NAK yes UC NoChange ignore no UC NoChange ignore no UC NoChange Stall yes ...
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... Changes made by SIE to Internal Registers and Mode Bits DTOG DVAL COUNT Setup In Out CY7C65113C 1 NoChange ACK yes Stall yes Stall yes UC NoChange ignore no UC NoChange ignore Stall yes ACK Mode Bits Response Intr ACK yes UC NoChange ignore yes UC NoChange ignore yes UC NoChange ignore no [6] (STALL = 0) UC ...
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... OUT Received Received Data Valid Byte Count Byte Count Byte Count Byte Count Bit 5 Bit 4 Bit 3 Bit ACK Mode Bit 3 Mode Bit 2 CY7C65113C Bit 1 Bit 0 Read/Write/B Default/ oth/–[7] Reset P0.1 P0.0 11111111 BBBBBBBB P1.1 P1.0 11111111 BBBBBBBB P2.1 P2.0 11111111 BBBBBBBB P3 ...
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... Force Low Force Low Force Low D–[4] D+[3] D–[3] D+[2] Watchdog USB Bus Power-on Suspend Interrupt Reset Reset Reset Enable Interrupt Sense CY7C65113C Bit 2 Bit 1 Bit 0 Read/Write/B Default/ oth/–[7] Reset Port 2 Port 1 00000000 BBBBBBBB Connect Connect Status Status Port 2 Port 1 ...
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... Power Dissipation..................................................... 500 mW Static Discharge Voltage .......................................... > 2000V Latch-up Current ................................................... > 200 mA Max Output Sink Current into Port 0, 1 ...................... 60 mA Max Output Sink Current into DAC[7:2] Pins.............. 0.5V CC Max Output Source Current from Port CY7C65113C USB-A Vbus D– D+ GND USB-A Vbus D– D+ GND ...
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... USB Upstream/Downstream Port 15 k ±5% to Gnd 1.5 k ± REF Including R Resistor ext General Purpose I/O (GPIO) All ports, low-to-high edge All ports, high-to-low edge 1.9 mA (all ports 0, below approximately 2.5V. CC CY7C65113C Min. Max. Unit 3.15 3.45 V –0.4 0 A 1 0.2 V 0.8 2 ...
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... Per Table 7-6 of revision 1.1 of USB specification. CLOCK D D Document #: 38-08002 Rev 6.0 MHz) OSC Description Clock Source [10] USB Full-speed Signaling / Timer Signals t CYC 90% 90% 10% CY7C65113C Min. Max. Unit 6 ±0.25% MHz 166.25 167. CYC 0. CYC 111 % 12 ±0.25% Mb/s 8.192 14.336 ms ...
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... Ordering Information Ordering Code PROM Size CY7C65113C-SXC 8 KB CY7C65113C-SXCT 8 KB Ordering Code Definitions xxxx Document #: 38-08002 Rev. *F Package Type 28-pin SOIC 28-pin SOIC-Tape and Reel T = Tape and Reel, Blank = Standard Temperature Range Commercial Package Code SOIC Part Number: 113C Family Code USB Hubs ...
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... Package Diagram Document #: 38-08002 Rev. *F Figure 36. 28-Pin (300-Mil) Molded SOIC CY7C65113C 51-85026 *F Page [+] Feedback ...
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... USB universal serial bus WDT watchdog timer Document #: 38-08002 Rev. *F Document Conventions Units of Measure Convention Description DC Direct current KB 1024 bytes Kbit 1024 bits kHz kilohertz k kilohm mA milli-ampere Mbps megabits per second ms milli seconds pF picofarad s microsecond V volts CY7C65113C Page [+] Feedback ...
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... Document History Page Document Title: CY7C65113C USB Hub with Microcontroller Document Number: 38-08002 Orig. of REV. ECN NO. Issue Date Change ** 109965 02/22/02 *A 120372 12/17/02 *B 124522 03/13/03 *C 368601 See ECN *D 429098 See ECN *E 3057657 10/13/10 *F 3207401 03/28/2011 Document #: 38-08002 Rev. *F Description of Change SZV ...
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... Purchase of I2C components from Cypress, or one of its sublicensed Associated Companies, conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. All product and company names mentioned in this document are the trademarks of their respective holders. cypress.com/go/plc Revised March 31, 2011 CY7C65113C PSoC Solutions psoc.cypress.com/solutions PSoC 1 ...