CY7C65113C-SXCT Cypress Semiconductor Corp, CY7C65113C-SXCT Datasheet - Page 16

• Manufacturer Part Number: CY7C65113C-SXCT
• Description: IC,MICROCONTROLLER,8-BIT,CMOS,SOP,28PIN,PLASTIC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C65113C-SXCT

• Applications: USB Hub/Microcontroller
• Core Processor: M8
• Program Memory Type: OTP (8 kB)
• Controller Series: USB Hub
• Ram Size: 256 x 8
• Interface: I²C, USB
• Number Of I /o: 11
• Voltage - Supply: 4 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (7.5mm Width)
• Processor Series: CY7C65xx
• Core: M8
• Data Bus Width: 16 bit
• Program Memory Size: 8 KB
• Data Ram Size: 256 B
• Interface Type: I2C
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 11
• Number Of Timers: 1
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: CY3654, CY3654-P03
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY3649 - PROGRAMMER HI-LO USB M8428-1339 - KIT LOW SPEED PERSONALITY BOARD
• Lead Free Status / Rohs Status: Details

Q1, Q2, and Q3 discussed below are the transistors referenced
in
■
■
■
Document #: 38-08002 Rev. *F
Table 4. GPIO Port Output Control Truth Table and Interrupt Polarity
Output LOW Mode: The pin’s Data Register is set to ‘0.’
Output HIGH Mode: The pin’s Data Register is set to 1 and
the Port Configuration Bits[1:0] is set to ‘10.’
Resistive Mode: The pin’s Data Register is set to 1 and the
Port Configuration Bits[1:0] is set to ‘11.’
Port Config Bit 1 Port Config Bit 0 Data Register Output Drive Strength Interrupt Enable Bit
Figure
Port 0 Interrupt Enable
Bit #
Bit Name
Read/Write
Reset
Port 1 Interrupt Enable
Bit #
Bit Name
Read/Write
Reset
Writing ‘0’ to the pin’s Data Register puts the pin in output
LOW mode, regardless of the contents of the Port Configura-
tion Bits[1:0]. In this mode, Q1 and Q2 are OFF. Q3 is ON.
The GPIO pin is driven LOW through Q3.
In this mode, Q1 and Q3 are OFF. Q2 is ON. The GPIO is
pulled up through Q2. The GPIO pin is capable of sourcing...
of current.
Q2 and Q3 are OFF. Q1 is ON. The GPIO pin is pulled up with
an internal 14kresistor. In resistive mode, the pin may serve
. The available GPIO drive strength are:
1
1
0
0
Reserved
P0.7 Intr
Enable
W
7
0
7
-
-
1
0
1
0
Reserved
P0.6 Intr
Enable
W
6
0
6
-
-
Reserved
0
1
0
1
0
1
0
1
P0.5 Intr
Figure 10. Port 1 Interrupt Enable
Figure 9.
Enable
W
5
0
5
-
-
.
Port 0 Interrupt Enable
Reserved
P0.4 Intr
Output HIGH
Output LOW
Output LOW
Output LOW
Output LOW
Enable
Resistive
W
4
0
4
-
-
Hi-Z
Hi-Z
■
GPIO Interrupt Enable Ports
Each GPIO pin can be individually enabled or disabled as an
interrupt source. The Port 0–1 Interrupt Enable Registers
provide this feature with an Interrupt Enable bit for each GPIO
pin.
During a reset, GPIO interrupts are disabled by clearing all of the
GPIO Interrupt Enable bits. Writing a ‘1’ to a GPIO Interrupt
Enable bit enables GPIO interrupts from the corresponding input
pin. All GPIO pins share a common interrupt, as discussed in
Section .
Hi-Z Mode: The pin’s Data Register is set to1 and Port Config-
uration Bits[1:0] is set either ‘00’ or ‘01.’
as an input. Reading the pin’s Data Register returns a logic
HIGH if the pin is not driven LOW by an external source.
Q1, Q2, and Q3 are all OFF. The GPIO pin is not driven inter-
nally. In this mode, the pin may serve as an input. Reading
the Port Data Register returns the actual logic value on the
port pins.
Reserved
P0.3 Intr
Enable
W
3
0
3
-
-
P0.2 Intr
P0.2 Intr
Enable
Enable
0
1
0
1
0
1
0
1
W
W
2
0
2
0
P0.1 Intr
P1.1 Intr
Enable
Enable
W
W
Interrupt Polarity
1
0
1
0
– (Falling Edge)
– (Falling Edge)
+ (Rising Edge)
CY7C65113C
Disabled
Disabled
Disabled
Disabled
Disabled
Address 0x04
Address 0x05
Page 16 of 48
P0.0 Intr
P1.0 Intr
Enable
Enable
W
W
0
0
0
0
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