CY7C65113C-SXCT Cypress Semiconductor Corp, CY7C65113C-SXCT Datasheet - Page 28

• Manufacturer Part Number: CY7C65113C-SXCT
• Description: IC,MICROCONTROLLER,8-BIT,CMOS,SOP,28PIN,PLASTIC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C65113C-SXCT

• Applications: USB Hub/Microcontroller
• Core Processor: M8
• Program Memory Type: OTP (8 kB)
• Controller Series: USB Hub
• Ram Size: 256 x 8
• Interface: I²C, USB
• Number Of I /o: 11
• Voltage - Supply: 4 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (7.5mm Width)
• Processor Series: CY7C65xx
• Core: M8
• Data Bus Width: 16 bit
• Program Memory Size: 8 KB
• Data Ram Size: 256 B
• Interface Type: I2C
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 11
• Number Of Timers: 1
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: CY3654, CY3654-P03
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY3649 - PROGRAMMER HI-LO USB M8428-1339 - KIT LOW SPEED PERSONALITY BOARD
• Lead Free Status / Rohs Status: Details

Bit [0..3]: Port x Enable (where x = 1..4)
Bit [4..7]: Reserved.
The Hub Ports Enable register is cleared to zero by reset or bus
reset to disable all downstream ports as the default condition. A
port is also disabled by internal hub hardware (enable bit
cleared) if babble is detected on that downstream port. Babble is
defined as:
Hub Downstream Ports Status and Control
Data transfer on hub downstream ports is controlled according
to the bit settings of the Hub Downstream Ports Control Register
(Figure 25). Each downstream port is controlled by two bits, as
Table 8. Control Bit Definition for Downstream Ports
.
Document #: 38-08002 Rev. *F
• Any non-idle downstream traffic on an enabled downstream
• Any downstream port with upstream connectivity established
Bit1
Control Bits
Hub Ports Force Low
Bit #
Bit Name
Read/Write
Reset
Hub Downstream Ports Control Register
Bit #
Bit Name
Read/Write
Reset
port at EOF2.
at EOF2 (i.e., no EOP received by EOF2).
0
0
1
1
Set to 1 if Port x is enabled; Set to 0 if Port x is disabled
Set to 0.
Bit 0
0
1
0
1
Control Bit 1
Force Low
Not Forcing (Normal USB Function)
Force Differential ‘1’ (D+ HIGH, D– LOW)
Force Differential ‘0’ (D+ LOW, D– HIGH)
Force SE0 state
D+[4]
Port 4
R/W
R/W
7
0
7
0
Control Bit 0
Force Low
Control Action
D–[4]
Port 4
R/W
R/W
6
0
6
0
Figure 25. Hub Downstream Ports Control Register
Figure 26. Hub Ports Force Low Register
Control Bit 1
Force Low
D+[3]
Port 3
R/W
R/W
5
0
5
0
Control Bit 0
Force Low
D–[3]
Port 3
R/W
R/W
4
0
4
0
defined in
Register is cleared upon reset or bus reset, and the reset state
is the state for normal USB traffic. Any downstream port being
forced must be marked as disabled (Figure 24) for proper
operation of the hub repeater.
Firmware should use this register for driving bus reset and
resume signaling to downstream ports. Controlling the port pins
through this register uses standard USB edge rate control
according to the speed of the port, set in the Hub Port Speed
Register.
The downstream USB ports are designed for connection of USB
devices, but can also serve as output ports under firmware
control. This allows unused USB ports to be used for functions
such as driving LEDs or providing additional input signals.
Pulling up these pins to voltages above V
flow into the pin.
This register is not reset by USB bus reset. These bits must be
cleared before going into suspend.
An alternate means of forcing the downstream ports is through
the Hub Ports Force Low Register (Figure 26) Register. With this
register the pins of the downstream ports can be individually
forced LOW, or left unforced. Unlike the Hub Downstream Ports
Control Register, above, the Force Low Register does not
produce standard USB edge rate control on the forced pins.
However, this register allows downstream port pins to be held
LOW in suspend. This register can be used to drive SE0 on all
downstream ports when unconfigured, as required in the USB
1.1 specification.
Control Bit 1
Force Low
D+[2]
Port 2
R/W
R/W
Table 8
3
0
3
0
below. The Hub Downstream Ports Control
Control Bit 0
Force Low
D–[2]
Port 2
R/W
R/W
2
0
2
0
Control Bit 1
Force Low
D+[1]
Port 1
R/W
R/W
1
0
1
0
REF
CY7C65113C
Address 0x4B
may cause current
Address 0x51
Control Bit 0
Force Low
Page 28 of 48
Port 1
D–[1]
R/W
R/W
0
0
0
0
[+] Feedback