CY7C65113C-SXCT Cypress Semiconductor Corp, CY7C65113C-SXCT Datasheet - Page 25

• Manufacturer Part Number: CY7C65113C-SXCT
• Description: IC,MICROCONTROLLER,8-BIT,CMOS,SOP,28PIN,PLASTIC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C65113C-SXCT

• Applications: USB Hub/Microcontroller
• Core Processor: M8
• Program Memory Type: OTP (8 kB)
• Controller Series: USB Hub
• Ram Size: 256 x 8
• Interface: I²C, USB
• Number Of I /o: 11
• Voltage - Supply: 4 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (7.5mm Width)
• Processor Series: CY7C65xx
• Core: M8
• Data Bus Width: 16 bit
• Program Memory Size: 8 KB
• Data Ram Size: 256 B
• Interface Type: I2C
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 11
• Number Of Timers: 1
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: CY3654, CY3654-P03
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY3649 - PROGRAMMER HI-LO USB M8428-1339 - KIT LOW SPEED PERSONALITY BOARD
• Lead Free Status / Rohs Status: Details

.
Refer to Sections and for more information of setting GPIO
interrupt polarity and enabling individual GPIO interrupts. If one
port pin has triggered an interrupt, no other port pins can cause
a GPIO interrupt until that port pin has returned to its inactive
(non-trigger) state or its corresponding port interrupt enable bit is
cleared. The USB Controller does not assign interrupt priority to
different port pins and the Port Interrupt Enable Registers are not
cleared during the interrupt acknowledge process.
I
The I
I
This generally involves reading the I
Register
loading/reading the I
writing the Processor Status and Control Register (Figure 17) to
initiate the subsequent transaction. The interrupt indicates that
status bits are stable and it is safe to read and write the I
registers. Refer to Section for details on the I
When enabled, the I
interrupts on completion of the following conditions. The refer-
enced bits are in the I
Document #: 38-08002 Rev. *F
1. In slave receive mode, after the slave receives a byte of data:
2. In slave receive mode, after a stop bit is detected: The
2
2
C-compatible bus to signal the need for firmware interaction.
C Interrupt
GPIO
Pin
The Addr bit is set, if this is the first byte since a start or restart
signal was sent by the external master. Firmware must read
or write the data register as necessary, then set the ACK, Xmit
MODE, and Continue/Busy bits appropriately for the next
byte.
Received Stop bit is set, if the stop bit follows a slave receive
transaction where the ACK bit was cleared to 0, no stop bit
detection occurs.
IRA
2
C interrupt occurs after various events on the
1 = Enable
0 = Disable
(Figure
16) to determine the cause of the interrupt,
2
2
C Data Register as appropriate, and finally
C-compatible state machines generate
2
C Status and Control Register.
Port Interrupt
Enable Register
Configuration
2
Register
M
U
X
C Status and Control
Port
2
C registers.
Figure 21. GPIO Interrupt Structure
1 = Enable
0 = Disable
2
C
(1 input per
OR Gate
GPIO pin)
(Bit 5, Register 0x20)
GPIO Interrupt
The Continue/Busy bit is cleared by hardware prior to interrupt
conditions 1 to 4. Once the Data Register has been read or
written, firmware should configure the other control bits and set
the Continue/Busy bit for subsequent transactions. Following an
interrupt from master mode, firmware should perform only one
write to the Status and Control Register that sets the
Continue/Busy bit, without checking the value of the
Continue/Busy bit. The Busy bit may otherwise be active and I
register contents may be changed by the hardware during the
transaction, until the I
3. In slave transmit mode, after the slave transmits a byte of
4. In master transmit mode, after the master sends a byte of
5. In master receive mode, after the master receives a byte of
6. When the master loses arbitration: This condition clears the
Global
Enable
data: The ACK bit indicates if the master that requested the
byte acknowledged the byte. If more bytes are to be sent,
firmware writes the next byte into the Data Register and then
sets the Xmit MODE and Continue/Busy bits as required.
data. Firmware should load the Data Register if necessary,
and set the Xmit MODE, MSTR MODE, and Continue/Busy
bits appropriately. Clearing the MSTR MODE bit issues a stop
signal to the I
data: Firmware should read the data and set the ACK and
Continue/Busy bits appropriately for the next byte. Clearing
the MSTR MODE bit at the same time causes the master state
machine to issue a stop signal to the I
leave the I2C-compatible hardware in the idle state.
MSTR MODE bit and sets the ARB Lost/Restart bit immedi-
ately and then waits for a stop signal on the I
bus to generate the interrupt.
1
GPIO Interrupt
Flip Flop
D
CLR
Q
2
C-compatible bus and return to the idle state.
2
C interrupt occurs.
Interrupt
Encoder
Priority
2
C-compatible bus and
CY7C65113C
2
Interrupt
IRQout
C-compatible
Vector
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2
C
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