CY7C65113C-SXCT Cypress Semiconductor Corp, CY7C65113C-SXCT Datasheet - Page 24

• Manufacturer Part Number: CY7C65113C-SXCT
• Description: IC,MICROCONTROLLER,8-BIT,CMOS,SOP,28PIN,PLASTIC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C65113C-SXCT

• Applications: USB Hub/Microcontroller
• Core Processor: M8
• Program Memory Type: OTP (8 kB)
• Controller Series: USB Hub
• Ram Size: 256 x 8
• Interface: I²C, USB
• Number Of I /o: 11
• Voltage - Supply: 4 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (7.5mm Width)
• Processor Series: CY7C65xx
• Core: M8
• Data Bus Width: 16 bit
• Program Memory Size: 8 KB
• Data Ram Size: 256 B
• Interface Type: I2C
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 11
• Number Of Timers: 1
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: CY3654, CY3654-P03
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY3649 - PROGRAMMER HI-LO USB M8428-1339 - KIT LOW SPEED PERSONALITY BOARD
• Lead Free Status / Rohs Status: Details

Interrupt Latency
Interrupt latency can be calculated from the following equation:
Interrupt latency = (Number of clock cycles remaining in the current instruction) +
For example, if a 5-clock cycle instruction such as JC is being
executed when an interrupt occurs, the first instruction of the
Interrupt Service Routine executes a minimum of 16 clocks
(1+10+5) or a maximum of 20 clocks (5+10+5) after the interrupt
is issued. For a 12-MHz internal clock (6-MHz crystal), 20 clock
periods is 20/12 MHz = 1.667 s.
USB Bus Reset Interrupt
The USB Controller recognizes a USB Reset when a Single
Ended Zero (SE0) condition persists on the upstream USB port
for 12–16 s. SE0 is defined as the condition in which both the
D+ line and the D– line are LOW. A USB Bus Reset may be
recognized for an SE0 as short as 12 s, but is always recog-
nized for an SE0 longer than 16 s. When a USB Bus Reset is
detected, bit 5 of the Processor Status and Control Register
(Figure 17) is set to record this event. In addition, the controller
clears the following registers:
SIE Section:.....USB Device Address Registers (0x10, 0x40)
Hub Section: ...................... Hub Ports Connect Status (0x48)
........................................................ Hub Ports Enable (0x49)
.........................................................Hub Ports Speed (0x4A)
.....................................................Hub Ports Suspend (0x4D)
...........................................Hub Ports Resume Status (0x4E)
................................................. Hub Ports SE0 Status (0x4F)
............................................................Hub Ports Data (0x50)
............................................. Hub Downstream Force (0x51).
A USB Bus Reset Interrupt is generated at the end of the USB
Bus Reset condition when the SE0 state is deasserted. If the
USB reset occurs during the start-up delay following a POR, the
delay is aborted as described in Section .
Document #: 38-08002 Rev. *F
(5 clock cycles for the JMP instruction)
Timer Interrupt
There are two periodic timer interrupts: the 128-s interrupt and
the 1.024-ms interrupt. The user should disable both timer inter-
rupts before going into the suspend mode to avoid possible
conflicts between servicing the timer interrupts first or the
suspend request first.
USB Endpoint Interrupts
There are five USB endpoint interrupts, one per endpoint. A USB
endpoint interrupt is generated after the USB host writes to a
USB endpoint FIFO or after the USB controller sends a packet
to the USB host. The interrupt is generated on the last packet of
the transaction (e.g., on the host’s ACK on an IN transfer, or on
the device ACK on an OUT transfer). If no ACK is received during
an IN transaction, no interrupt is generated.
USB Hub Interrupt
A USB hub interrupt is generated by the hardware after a
connect/disconnect change, babble, or a resume event is
detected by the USB repeater hardware. The babble and resume
events are additionally gated by the corresponding bits of the
Hub Port Enable Register (Figure 24). The connect/disconnect
event on a port does not generate an interrupt if the SIE does not
drive the port (i.e., the port is being forced).
GPIO Interrupt
Each of the GPIO pins can generate an interrupt, if enabled. The
interrupt polarity can be programmed for each GPIO port as part
of the GPIO configuration. All of the GPIO pins share a single
interrupt vector, which means the firmware needs to read the
GPIO ports with enabled interrupts to determine which pin or pins
caused an interrupt. A block diagram of the GPIO interrupt logic
is shown in
Figure
(10 clock cycles for the CALL instruction) +
.
CY7C65113C
Page 24 of 48
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