CY7C65113C-SXCT Cypress Semiconductor Corp, CY7C65113C-SXCT Datasheet - Page 23

• Manufacturer Part Number: CY7C65113C-SXCT
• Description: IC,MICROCONTROLLER,8-BIT,CMOS,SOP,28PIN,PLASTIC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C65113C-SXCT

• Applications: USB Hub/Microcontroller
• Core Processor: M8
• Program Memory Type: OTP (8 kB)
• Controller Series: USB Hub
• Ram Size: 256 x 8
• Interface: I²C, USB
• Number Of I /o: 11
• Voltage - Supply: 4 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (7.5mm Width)
• Processor Series: CY7C65xx
• Core: M8
• Data Bus Width: 16 bit
• Program Memory Size: 8 KB
• Data Ram Size: 256 B
• Interface Type: I2C
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 11
• Number Of Timers: 1
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: CY3654, CY3654-P03
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY3649 - PROGRAMMER HI-LO USB M8428-1339 - KIT LOW SPEED PERSONALITY BOARD
• Lead Free Status / Rohs Status: Details

Interrupt Vectors
The Interrupt Vectors supported by the USB Controller are listed in
has the highest priority, and the highest-numbered interrupt (I
Although Reset is not an interrupt, the first instruction executed after a reset is at PROM address 0x0000h—which corresponds to the
first entry in the Interrupt Vector Table. Because the JMP instruction is two bytes long, the interrupt vectors occupy two bytes.
Document #: 38-08002 Rev. *F
Table 7. Interrupt Vector Assignments
AddrA ENP2 Int
USB Reset Int
Interrupt Vector Number
I
2
C Int
Not Applicable
1
1
1
10
11
12
1
2
3
4
5
6
7
8
9
CLK
D
D
CLK
CLK
D
CLR
CLR
CLR
Q
Q
Q
(Reg 0x21)
Enable [2]
(Reg 0x20)
(Reg 0x20)
Enable [0]
Enable [6]
Figure 20. Interrupt Controller Function Diagram
ROM Address
0x000C
0x0000
0x0002
0x0004
0x0006
0x0008
0x000A
0x000E
0x0010
0x0012
0x0014
0x0016
0x0018
USB Reset IRQ
AddrA EP0 IRQ
AddrA EP1 CLR
AddrA EP1 IRQ
AddrA EP2 CLR
AddrA EP2 IRQ
AddrB EP0 IRQ
AddrB EP1 IRQ
DAC IRQ
128-s CLR
128-s IRQ
1-ms CLR
1-ms IRQ
AddrA EP0 CLR
AddrB EP0 CLR
AddrB EP1 CLR
Hub CLR
Hub IRQ
DAC CLR
GPIO CLR
GPIO IRQ
I
USB Reset Clear Interrupt
I
2
2
2
Interrupt Priority Encoder
C CLR
C interrupt) has the lowest priority.
C IRQ
Table
7. The lowest-numbered interrupt (USB Bus Reset interrupt)
Execution after Reset begins here
USB Bus Reset interrupt
128-s timer interrupt
1.024-ms timer interrupt
USB Address A Endpoint 0 interrupt
USB Address A Endpoint 1 interrupt
USB Address A Endpoint 2 interrupt
USB Address B Endpoint 0 interrupt
USB Address B Endpoint 1 interrupt
USB Hub interrupt
DAC interrupt
GPIO interrupt
I
2
C interrupt
IRQout
Vector
Acknowledge
To CPU
CPU
Interrupt
Interrupt
Enable
Global
CLR
Bit
Function
Controlled by DI, EI, and
RETI Instructions
CY7C65113C
IRQ Sense
Int Enable
Sense
Page 23 of 48
IRQ
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