CY7C65113C-SXCT Cypress Semiconductor Corp, CY7C65113C-SXCT Datasheet - Page 20

• Manufacturer Part Number: CY7C65113C-SXCT
• Description: IC,MICROCONTROLLER,8-BIT,CMOS,SOP,28PIN,PLASTIC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C65113C-SXCT

• Applications: USB Hub/Microcontroller
• Core Processor: M8
• Program Memory Type: OTP (8 kB)
• Controller Series: USB Hub
• Ram Size: 256 x 8
• Interface: I²C, USB
• Number Of I /o: 11
• Voltage - Supply: 4 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (7.5mm Width)
• Processor Series: CY7C65xx
• Core: M8
• Data Bus Width: 16 bit
• Program Memory Size: 8 KB
• Data Ram Size: 256 B
• Interface Type: I2C
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 11
• Number Of Timers: 1
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: CY3654, CY3654-P03
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY3649 - PROGRAMMER HI-LO USB M8428-1339 - KIT LOW SPEED PERSONALITY BOARD
• Lead Free Status / Rohs Status: Details

Bit 4: ACK
Bit 3: Addr
Bit 2: ARB Lost/Restart
Processor Status and Control Register
Bit 0: Run
Bit 1: Reserved
Bit 2: Interrupt Enable Sense
Bit 3: Suspend
Document #: 38-08002 Rev. *F
Processor Status and Control
Bit #
Bit Name
Read/Write
Reset
start bits, as these cases always cause transmit mode for
the first byte.
This bit is set or cleared by firmware during receive oper-
ation to indicate if the hardware should generate an ACK
signal on the I
generates an ACK (SDA LOW) on the I2C-compatible bus
at the ACK bit time. During transmits (Xmit Mode = 1), this
bit should be cleared.
This bit is set by the I
byte of a slave receive transaction, after an I
restart. The Addr bit is cleared when the firmware sets the
Continue bit. This bit allows the firmware to recognize
when the master has lost arbitration, and in slave mode it
allows the firmware to recognize that a start or restart has
occurred.
This bit is manipulated by the HALT instruction. When Halt
is executed, all the bits of the Processor Status and Control
Register are cleared to 0. Since the run bit is cleared, the
processor stops at the end of the current instruction. The
processor remains halted until an appropriate reset occurs
(power-on or Watchdog). This bit should normally be writ-
ten as a ‘1.’
Bit 1 is reserved and must be written as a zero.
This bit indicates whether interrupts are enabled or dis-
abled. Firmware has no direct control over this bit as writ-
ing a zero or one to this bit position has no effect on inter-
rupts. A ‘0’ indicates that interrupts are masked off and a
‘1’ indicates that the interrupts are enabled. This bit is fur-
ther gated with the bit settings of the Global Interrupt En-
able Register (Figure 18) and USB End Point Interrupt En-
able Register (Figure 19). Instructions DI, EI, and RETI
manipulate the state of this bit.
Pending
2
IRQ
C-compatible bus. Writing a 1 to this bit
R
7
0
2
C-compatible block during the first
Watchdog
Reset
R/W
6
0
Figure 17. Processor Status and Control Register
USB Bus
Interrupt
Reset
R/W
5
0
2
C start or
Power-on
Reset
R/W
4
1
Bit 1: Receive Stop
Bit 0: I
Bit 4: Power-on Reset
Bit 5: USB Bus Reset Interrupt
This bit is valid as a status bit (ARB Lost) after master
mode transactions. In master mode, set this bit (along with
the Continue and MSTR Mode bits) to perform an I
start sequence. The I
be written to the data register before setting the Continue
bit. To prevent false ARB Lost signals, the Restart bit is
cleared by hardware during the restart sequence.
This bit is set when the slave is in receive mode and de-
tects a stop bit on the bus. The Receive Stop bit is not set
if the firmware terminates the I
knowledging the previous byte transmitted on the
I
the Continue bit and clears the ACK bit.
Set this bit to override GPIO definition with I
function on the two I
cleared, these pins are free to function as GPIOs. In
I
mode, independent of the GPIO configuration setting.
Writing a ‘1’ to the Suspend bit halts the processor and
cause the microcontroller to enter the suspend mode that
significantly reduces power consumption. A pending, en-
abled interrupt or USB bus activity causes the device to
come out of suspend. After coming out of suspend, the
device resumes firmware execution at the instruction fol-
lowing the IOWR which put the part into suspend. An
IOWR attempting to put the part into suspend is ignored if
USB bus activity is present. See Section for more details
on suspend mode operation.
The Power-on Reset is set to ‘1’ during a power-on reset.
The firmware can check bits 4 and 6 in the reset handler
to determine whether a reset was caused by a power-on
condition or a Watchdog timeout. A POR event may be
followed by a Watchdog reset before firmware begins ex-
ecuting, as explained below.
The USB Bus Reset Interrupt bit is set when the USB Bus
Reset is detected on receiving a USB Bus Reset signal on
the upstream port. The USB Bus Reset signal is a sin-
gle-ended zero (SE0) that lasts from 12 to 16 s. An SE0
2
2
2
C Enable
C-compatible bus, e.g., in receive mode if firmware sets
C-compatible mode, the two pins operate in open drain
Suspend
R/W
3
0
Interrupt
Enable
Sense
R
2
0
2
2
C target address for the restart must
C-compatible pins. When this bit is
Reserved
2
R/W
C transaction by not ac-
1
0
CY7C65113C
Address 0xFF
2
Page 20 of 48
C-compatible
Run
R/W
0
1
2
C re-
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