CY7C65113C-SXCT Cypress Semiconductor Corp, CY7C65113C-SXCT Datasheet - Page 12

• Manufacturer Part Number: CY7C65113C-SXCT
• Description: IC,MICROCONTROLLER,8-BIT,CMOS,SOP,28PIN,PLASTIC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C65113C-SXCT

• Applications: USB Hub/Microcontroller
• Core Processor: M8
• Program Memory Type: OTP (8 kB)
• Controller Series: USB Hub
• Ram Size: 256 x 8
• Interface: I²C, USB
• Number Of I /o: 11
• Voltage - Supply: 4 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (7.5mm Width)
• Processor Series: CY7C65xx
• Core: M8
• Data Bus Width: 16 bit
• Program Memory Size: 8 KB
• Data Ram Size: 256 B
• Interface Type: I2C
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 11
• Number Of Timers: 1
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: CY3654, CY3654-P03
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY3649 - PROGRAMMER HI-LO USB M8428-1339 - KIT LOW SPEED PERSONALITY BOARD
• Lead Free Status / Rohs Status: Details

The XTALIN and XTALOUT are the clock pins to the microcon-
troller. The user can connect an external oscillator or a crystal to
these pins. When using an external crystal, keep PCB traces
between the chip leads and crystal as short as possible (less
than 2 cm). A 6-MHz fundamental frequency parallel resonant
crystal can be connected to these pins to provide a reference
frequency for the internal PLL. The two internal 30-pF load caps
appear in series to the external crystal and would be equivalent
to a 15-pF load. Therefore, the crystal must have a required load
capacitance of about 15–18 pF. A ceramic resonator does not
allow the microcontroller to meet the timing specifications of full
speed USB and therefore a ceramic resonator is not recom-
mended with these parts.
An external 6-MHz clock can be applied to the XTALIN pin if the
XTALOUT pin is left open. Grounding the XTALOUT pin when
driving XTALIN with an oscillator does not work because the
internal clock is effectively shorted to ground.
Reset
The CY7C65113C supports two resets: POR and WDR. Each of
these resets causes:
The occurrence of a reset is recorded in the Processor Status
and Control Register, as described in Section. Bits 4 and 6 are
used to record the occurrence of POR and WDR respectively.
Firmware can interrogate these bits to determine the cause of a
reset.
Document #: 38-08002 Rev. *F
• all registers to be restored to their default states
• the USB device addresses to be set to 0
• all interrupts to be disabled
• the PSP and DSP to be set to memory address 0x00.
Program execution starts at ROM address 0x0000 after a reset.
Although this looks like interrupt vector 0, there is an important
difference. Reset processing does NOT push the program
counter, carry flag, and zero flag onto program stack. The
firmware reset handler should configure the hardware before the
“main” loop of code. Attempting to execute a RET or RETI in the
firmware reset handler causes unpredictable execution results.
Power-on Reset
When V
and the CY7C65113C enters a “semi-suspend” state. During the
semi-suspend state, which is different from the suspend state
defined in the USB specification, the oscillator and all other
blocks of the part are functional, except for the CPU. This
semi-suspend time ensures that both a valid V
and that the internal PLL has time to stabilize before full
operation begins. When the V
2.5V, and the oscillator is stable, the POR is deasserted and the
on-chip timer starts counting. The first 1 ms of suspend time is
not interruptible, and the semi-suspend state continues for an
additional 95 ms unless the count is bypassed by a USB Bus
Reset on the upstream port. The 95 ms provides time for V
stabilize at a valid operating voltage before the chip executes
code.
If a USB Bus Reset occurs on the upstream port during the 95
ms semi-suspend time, the semi-suspend state is aborted and
program execution begins immediately from address 0x0000. In
this case, the Bus Reset interrupt is pending but not serviced
until firmware sets the USB Bus Reset Interrupt Enable bit (Bit 0,
Figure 18) and enables interrupts with the EI command.
The POR signal is asserted whenever V
imately 2.5V, and remains asserted until V
level again. Behavior is the same as described above.
CC
is first applied to the chip, the POR signal is asserted
CC
has risen above approximately
CC
CY7C65113C
CC
drops below approx-
CC
rises above this
level is reached
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