CY7C65113C-SXCT Cypress Semiconductor Corp, CY7C65113C-SXCT Datasheet - Page 18

• Manufacturer Part Number: CY7C65113C-SXCT
• Description: IC,MICROCONTROLLER,8-BIT,CMOS,SOP,28PIN,PLASTIC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C65113C-SXCT

• Applications: USB Hub/Microcontroller
• Core Processor: M8
• Program Memory Type: OTP (8 kB)
• Controller Series: USB Hub
• Ram Size: 256 x 8
• Interface: I²C, USB
• Number Of I /o: 11
• Voltage - Supply: 4 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (7.5mm Width)
• Processor Series: CY7C65xx
• Core: M8
• Data Bus Width: 16 bit
• Program Memory Size: 8 KB
• Data Ram Size: 256 B
• Interface Type: I2C
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 11
• Number Of Timers: 1
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: CY3654, CY3654-P03
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY3649 - PROGRAMMER HI-LO USB M8428-1339 - KIT LOW SPEED PERSONALITY BOARD
• Lead Free Status / Rohs Status: Details

Internal hardware supports communication with external devices through an I
discussed in detail in Section .
the SCL (clock) and SDA (data) pins on Port 1 as shown in
for I
recommended.
.
Table 5. I
I2C-compatible Controller
The I2C-compatible block provides a versatile two-wire commu-
nication with external devices, supporting master, slave, and
multi-master modes of operation. The I2C-compatible block
functions by handling the low-level signaling in hardware, and
issuing interrupts as needed to allow firmware to take appro-
priate action during transactions. While waiting for firmware
response, the hardware keeps the I2C-compatible bus idle if
necessary.
The I2C-compatible block generates an interrupt to the micro-
controller at the end of each received or transmitted byte, when
a stop bit is detected by the slave when in receive mode, or when
arbitration is lost. Details of the interrupt responses are given in
Section .
The I2C-compatible interface consists of two registers, an I
Data Register (Figure 15) and an I
Register
separate read and write registers. Generally, the I
Document #: 38-08002 Rev. *F
Note
I
3. I
2
I2C Data
Bit #
Bit Name
Read/Write
Reset
C Configuration Register
I
Bit #
Bit Name
Read/Write
Reset
2
2
2
C Configuration
C function, the internal pull ups on the pins are disabled. Addition of an external weak pull-up resistors on SCL and SDA is
C-compatible function must be separately enabled, as described in Section .
I
2
C Position (Bit7, Figure 14)
(Figure
2
C Port Configuration
16). The I
I
2
I
C Position
2
C Data 7
R/W
R/W
0
7
0
7
X
2
C Data Register is implemented as
[3]
The I
Reserved
I
2
2
C Data 6
R/W
C Status and Control
R/W
6
0
6
X
2
C Position bit (Bit 7, Figure 14) and I
Figure 14. I
Reserved
I
2
C Data 5
2
R/W
R/W
I
C Status and
2
Figure 15. I
X
5
0
5
C Port Width (Bit1, Figure 14)
2
2
C Configuration Register
Table
C
Reserved
I
2
C Data 4
2
R/W
R/W
C Data Register
X
4
0
4
5. These bits are cleared on reset. When the GPIO is configured
0
Control Register should only be monitored after the I
as all bits are valid at that time. Polling this register at other times
could read misleading bit status if a transaction is underway.
The I
I
selection is determined by settings in the I
Register (Section ). Once the I
enabled by setting the I
Control Register (bit 0,
corresponding GPIO port is placed in Open Drain mode,
regardless of the settings of the GPIO Configuration Register. In
Open Drain mode, the GPIO pin outputs LOW if the pin’s Data
Register is ‘0’, and the pin is in Hi-Z mode if the pin’s Data
Register is ‘1’. The electrical characteristics of the
I
that the I
All control of the I
performed by the I
2
2
C SDA data is connected to bit 1 GPIO port 1. The port
C-compatible interface is the same as that of GPIO port 1. Note
2
C clock (SCL) is connected to bit 0 of GPIO port 1, and the
2
Reserved
I
2
C Port Width bit (Bit 1, Figure 14) select the locations of
C Data 3
OL
2
R/W
R/W
C-compatible interface. I
X
3
0
3
(max) is 2 mA @ V
2
2
C clock (SCL) and data (SDA) lines is
C-compatible block.
I
Reserved
2
C Data 2
2
Figure
R/W
R/W
I
C Enable bit of the I
2
X
2
0
2
C on P1[1:0], 0:SCL, 1:SDA
16), the two LSB ([1:0]) of the
2
OL
C-compatible functionality is
I
2
= 2.0V for port 1.
C Position
2
I
C-compatible function is
2
I
2
C Data 1
Width
C Port
R/W
R/W
X
1
0
1
2
CY7C65113C
C Port Configuration
2
C Status and
Address 0x09
Address 0x29
I
Reserved
Page 18 of 48
2
C Data 0
2
R/W
R/W
C interrupt,
X
0
0
0
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