CY7C65113C-SXCT Cypress Semiconductor Corp, CY7C65113C-SXCT Datasheet - Page 17

• Manufacturer Part Number: CY7C65113C-SXCT
• Description: IC,MICROCONTROLLER,8-BIT,CMOS,SOP,28PIN,PLASTIC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C65113C-SXCT

• Applications: USB Hub/Microcontroller
• Core Processor: M8
• Program Memory Type: OTP (8 kB)
• Controller Series: USB Hub
• Ram Size: 256 x 8
• Interface: I²C, USB
• Number Of I /o: 11
• Voltage - Supply: 4 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (7.5mm Width)
• Processor Series: CY7C65xx
• Core: M8
• Data Bus Width: 16 bit
• Program Memory Size: 8 KB
• Data Ram Size: 256 B
• Interface Type: I2C
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 11
• Number Of Timers: 1
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: CY3654, CY3654-P03
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY3649 - PROGRAMMER HI-LO USB M8428-1339 - KIT LOW SPEED PERSONALITY BOARD
• Lead Free Status / Rohs Status: Details

12-bit Free-Running Timer
The 12-bit timer operates with a 1-s tick, provides two interrupts (128 s and 1.024 ms) and allows the firmware to directly time
events that are up to 4 ms in duration. The lower eight bits of the timer can be read directly by the firmware. Reading the lower eight
bits latches the upper four bits into a temporary register. When the firmware reads the upper four bits of the timer, it is actually reading
the count stored in the temporary register. The effect of this is to ensure a stable 12-bit timer value can be read, even when the two
reads are separated in time.
Bit [7:0]: Timer lower eight bits
Bit [3:0]: Timer higher nibble
Bit [7:4]: Reserved.
Document #: 38-08002 Rev. *F
Bit #
Bit Name
Read/Write
Reset
Timer LSB
Bit #
Bit Name
Read/Write
Reset
Timer MSB
11
L3
D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
Timer Bit 7
Reserved
10 9
L2
R
7
0
7
–
0
L1 L0
TimerBit 6
Reserved
8
R
6
0
6
–
0
7
Timer Bit 5
6
Reserved
Figure 13. Timer Block Diagram
Figure 12. Timer MSB Register.
Figure 11. Timer LSB Register
R
5
0
5
–
0
5
4
Timer Bit 4
Reserved
R
4
0
4
–
0
3
2
Timer Bit 11 Timer Bit 10
Timer Bit 3
1
R
R
3
0
3
0
0
8
Timer Bit 2
R
R
2
0
2
0
1.024-ms interrupt
128-
1 MHz clock
To Timer Registers

s interrupt
Timer Bit 9
Timer Bit 1
R
R
1
0
1
0
CY7C65113C
Address 0x24
Address 0x25
Timer Bit 0
Timer Bit 8
Page 17 of 48
R
R
0
0
0
0
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