CY7C65113C-SXCT Cypress Semiconductor Corp, CY7C65113C-SXCT Datasheet - Page 29

• Manufacturer Part Number: CY7C65113C-SXCT
• Description: IC,MICROCONTROLLER,8-BIT,CMOS,SOP,28PIN,PLASTIC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C65113C-SXCT

• Applications: USB Hub/Microcontroller
• Core Processor: M8
• Program Memory Type: OTP (8 kB)
• Controller Series: USB Hub
• Ram Size: 256 x 8
• Interface: I²C, USB
• Number Of I /o: 11
• Voltage - Supply: 4 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (7.5mm Width)
• Processor Series: CY7C65xx
• Core: M8
• Data Bus Width: 16 bit
• Program Memory Size: 8 KB
• Data Ram Size: 256 B
• Interface Type: I2C
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 11
• Number Of Timers: 1
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: CY3654, CY3654-P03
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY3649 - PROGRAMMER HI-LO USB M8428-1339 - KIT LOW SPEED PERSONALITY BOARD
• Lead Free Status / Rohs Status: Details

The data state of downstream ports can be read through the HUB
Ports SE0 Status Register (Figure 27) and the Hub Ports Data
Register (Figure 28). The data read from the Hub Ports Data
Register is the differential data only and is independent of the
settings of the Hub Ports Speed Register (Figure ). When the
.
Bit [0..3]: Port x SE0 Status (where x = 1..4).
Bit [0..3]: Port x Diff Data (where x = 1..4).
Bit [4..7]: Reserved.
Downstream Port Suspend and Resume
The Hub Ports Suspend Register (Figure 29) and Hub Ports
Resume Status Register (Figure 30) indicate the suspend and
resume conditions on downstream ports. The suspend register
must be set by firmware for any ports that are selectively
suspended. Also, this register is only valid for ports that are
selectively suspended.
If a port is marked as selectively suspended, normal USB traffic
is not sent to that port. Resume traffic is also prevented from
going to that port, unless the Resume comes from the selectively
suspended port. If a resume condition is detected on the port,
hardware reflects a Resume back to the port, sets the Resume
bit in the Hub Ports Resume Register, and generates a hub
interrupt.
Document #: 38-08002 Rev. *F
Hub Ports Data
Bit #
Bit Name
Read/Write
Reset
Hub Ports SE0 Status
Bit #
Bit Name
Read/Write
Reset
Set to 1 if a SE0 is output on the Port x bus; Set to 0 if a
Non-SE0 is output on the Port x bus.
Set to 1 if D+ > D- (forced differential 1, if signal is differ-
ential, i.e. not a SE0 or SE1). Set to 0 if D- > D+ (forced
differential 0, if signal is differential, i.e. not a SE0 or SE1).
Set to 0.
Reserved
Reserved
R
R
7
0
7
0
Reserved
Reserved
R
R
6
0
6
0
Figure 27. Hub Ports SE0 Status Register
Figure 28.
Reserved
Reserved
R
R
5
0
5
0
.
Hub Ports Data Register
Reserved
Reserved
R
R
4
0
4
0
SE0 condition is sensed on a downstream port, the corre-
sponding bits of the Hub Ports Data Register hold the last differ-
ential data state before the SE0. Hub Ports SE0 Status Register
and Hub Ports Data Register are cleared upon reset or bus reset.
Bit [4..7]: Reserved.
If a disconnect occurs on a port marked as selectively
suspended, the suspend bit is cleared.
The Device Remote Wakeup bit (bit 7) of the Hub Ports Suspend
Register controls whether or not the resume signal is propagated
by the hub after a connect or a disconnect event. If the Device
Remote Wakeup bit is set, the hub will automatically propagate
the resume signal after a connect or a disconnect event. If the
Device Remote Wakeup bit is cleared, the hub will not propagate
the resume signal. The setting of the Device Remote Wakeup
flag has no impact on the propagation of the resume signal after
a downstream remote wakeup event. The hub will automatically
propagate the resume signal after a remote wakeup event,
regardless of the state of the Device Remote wakeup bit. The
state of this bit has no impact on the generation of the hub
interrupt.
A resume bit is set automatically when hardware detects a
resume condition on a selectively suspended downstream port.
The resume condition is a differential ‘1’ for a low-speed device
and a differential ‘0’ for a full-speed device.
These registers are cleared on reset or USB bus reset.
Set to 0
SE0 Status
Port 4 Diff.
Port 4
Data
R
R
3
0
3
0
SE0 Status
Port 3 Diff.
Port 3
Data
R
2
0
R
2
0
SE0 Status
Port 2 Diff.
Port 2
Data
R
1
0
R
1
0
Address 0x4F
CY7C65113C
ADDRESS 0x50
SE0 Status
Port 1 Diff.
Page 29 of 48
Port 1
Data
R
0
0
R
0
0
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