CY7C65113C-SXCT Cypress Semiconductor Corp, CY7C65113C-SXCT Datasheet - Page 21

• Manufacturer Part Number: CY7C65113C-SXCT
• Description: IC,MICROCONTROLLER,8-BIT,CMOS,SOP,28PIN,PLASTIC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C65113C-SXCT

• Applications: USB Hub/Microcontroller
• Core Processor: M8
• Program Memory Type: OTP (8 kB)
• Controller Series: USB Hub
• Ram Size: 256 x 8
• Interface: I²C, USB
• Number Of I /o: 11
• Voltage - Supply: 4 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (7.5mm Width)
• Processor Series: CY7C65xx
• Core: M8
• Data Bus Width: 16 bit
• Program Memory Size: 8 KB
• Data Ram Size: 256 B
• Interface Type: I2C
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 11
• Number Of Timers: 1
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: CY3654, CY3654-P03
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY3649 - PROGRAMMER HI-LO USB M8428-1339 - KIT LOW SPEED PERSONALITY BOARD
• Lead Free Status / Rohs Status: Details

Bit 6: Watchdog Reset
Bit 7: IRQ Pending
During power-up, the Processor Status and Control Register is
set to 00010001, which indicates a POR (bit 4 set) has occurred
and no interrupts are pending (bit 7 clear). During the 96-ms
suspend at start-up (explained in Section ), a Watchdog Reset
also occurs unless this suspend is aborted by an upstream SE0
Bit 0: USB Bus RST Interrupt Enable
Bit 1:128-s Interrupt Enable
Bit 2: 1.024-ms Interrupt Enable
Bit 3: USB Hub Interrupt Enable
Document #: 38-08002 Rev. *F
USB Endpoint Interrupt Enable
Bit #
Bit Name
Read/Write
Reset
Global Interrupt Enable Register
Bit #
Bit Name
Read/Write
Reset
is defined as the condition in which both the D+ line and
the D– line are LOW at the same time.
The Watchdog Reset is set during a reset initiated by the
Watchdog Timer. This indicates the Watchdog Timer went
for more than t
clears. This can occur with a POR event, as noted below.
The IRQ pending, when set, indicates that one or more of
the interrupts has been recognized as active. An interrupt
remains pending until its interrupt enable bit is set
(Figure 18, Figure 19) and interrupts are globally enabled.
At that point, the internal interrupt handling sequence
clears this bit until another interrupt is detected as pending.
1 = Enable Interrupt on a USB Bus Reset; 0 = Disable
interrupt on a USB Bus Reset (Refer to section ).
1 = Enable Timer interrupt every 128 s; 0 = Disable Timer
Interrupt for every 128 s.
1 = Enable Timer interrupt every 1.024 ms; 0 = Disable
Timer Interrupt every 1.024 ms.
Reserved
Reserved
WATCH
7
–
–
7
–
–
(8 ms minimum) between Watchdog
I
2
Reserved
C Interrupt
Enable
R/W
6
0
6
–
–
Figure 19. USB Endpoint Interrupt Enable Register.
Figure 18. Global Interrupt Enable Register
Reserved
Interrupt
Enable
GPIO
R/W
5
0
5
–
–
Reserved
Interrupt
Enable
EPB1
R/W
X
4
4
0
-
before 8 ms. If a WDR occurs during the power-up suspend
interval, firmware reads 01010001 from the Status and Control
Register after power-up. Normally, the POR bit should be cleared
so a subsequent WDR can be clearly identified. If an upstream
bus reset is received before firmware examines this register, the
Bus Reset bit may also be set.
During a Watchdog Reset, the Processor Status and Control
Register is set to 01XX0001, which indicates a Watchdog Reset
(bit 6 set) has occurred and no interrupts are pending (bit 7
clear). The Watchdog Reset does not effect the state of the POR
and the Bus Reset Interrupt bits.
Interrupts
Interrupts are generated by GPIO pins, internal timers,
I
conditions. All interrupts are maskable by the Global Interrupt
Enable Register and the USB End Point Interrupt Enable
Register. Writing a ‘1’ to a bit position enables the interrupt
associated with that bit position.
Bit 4: Reserved.
Bit 5: GPIO Interrupt Enable
Bit 6: I
Bit 7: Reserved
2
C-compatible operation, internal USB hub and USB traffic
1 = Enable Interrupt on a Hub status change; 0 = Disable
interrupt due to hub status change. (Refer to section .)
1 = Enable Interrupt on falling/rising edge on any GPIO; 0
= Disable Interrupt on falling/rising edge on any GPIO (Re-
fer to section , and .).
1 = Enable Interrupt on I2C related activity; 0 = Disable I2C
related activity interrupt. (Refer to section .)
2
USB Hub
C Interrupt Enable
Interrupt
Interrupt
Enable
Enable
R/W
EPB0
R/W
3
0
3
0
1.024-ms
Interrupt
Interrupt
Enable
Enable
EPA2
R/W
R/W
2
0
2
0
Interrupt
Interrupt
Enable
Enable
128-s
EPA1
R/W
R/W
1
0
Address 0X20
1
0
CY7C65113C
Address 0X21
Page 21 of 48
USB Bus
Interrupt
Interrupt
Enable
Enable
EPA0
RST
R/W
R/W
0
0
0
0
[+] Feedback