CY7C65113C-SXCT Cypress Semiconductor Corp, CY7C65113C-SXCT Datasheet - Page 36

• Manufacturer Part Number: CY7C65113C-SXCT
• Description: IC,MICROCONTROLLER,8-BIT,CMOS,SOP,28PIN,PLASTIC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C65113C-SXCT

• Applications: USB Hub/Microcontroller
• Core Processor: M8
• Program Memory Type: OTP (8 kB)
• Controller Series: USB Hub
• Ram Size: 256 x 8
• Interface: I²C, USB
• Number Of I /o: 11
• Voltage - Supply: 4 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (7.5mm Width)
• Processor Series: CY7C65xx
• Core: M8
• Data Bus Width: 16 bit
• Program Memory Size: 8 KB
• Data Ram Size: 256 B
• Interface Type: I2C
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 11
• Number Of Timers: 1
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: CY3654, CY3654-P03
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY3649 - PROGRAMMER HI-LO USB M8428-1339 - KIT LOW SPEED PERSONALITY BOARD
• Lead Free Status / Rohs Status: Details

endpoints reset to the disabled mode (0000). Firmware normally
enables the endpoint mode after a SetConfiguration request.
Any SETUP packet to an enabled endpoint with mode set to
accept SETUPs will be changed by the SIE to 0001 (NAKing INs
and OUTs). Any mode set to accept a SETUP will send an ACK
handshake to a valid SETUP token.
Table 12. Decode table for
The response of the SIE can be summarized as follows:
Document #: 38-08002 Rev. *F
1. The SIE will only respond to valid transactions, and will ignore
2. The SIE will generate an interrupt when a valid transaction is
3. An incoming Data packet is valid if the count is < Endpoint
4. An IN will be ignored by an OUT configured endpoint and visa
5. The IN and OUT PID status is updated at the end of a trans-
6. The SETUP PID status is updated at the beginning of the Data
7. The entire Endpoint 0 mode register and the Count register
3
Endpoint Mode
encoding
Legend:
non-valid ones.
completed or when the FIFO is corrupted. FIFO corruption
occurs during an OUT or SETUP transaction to a valid internal
address, that ends with a non-valid CRC.
Size + 2 (includes CRC) and passes all error checking;
versa.
action.
packet phase.
are locked to CPU writes at the end of any transaction to that
2
1
0
Received Token
(SETUP/IN/OUT)
Token
TX: transmit
RX: receive
x: don’t care
count
The number of received bytes
available for Control endpoint only
Properties of Incoming
Table
Packets
buffer
The quality status of the DMA buffer
UC : unchanged
TX0:Transmit 0 length packet
13: “Details of Modes for Differing Traffic Condition
dval
The validity of the received data
Changes to the Internal Register made by the SIE on receiving an incoming packet
DTOG
Data0/1 (bit7 Figure 17-4)
Data Valid (bit 6, Figure 17-4)
DVAL
Byte Count (bits 0..5, Figure 17-4)
COUNT
The control endpoint has three status bits for identifying the
token type received (SETUP, IN, or OUT), but the endpoint must
be placed in the correct mode to function as such. Non-control
endpoints should not be placed into modes that accept SETUPs.
Note that most modes that control transactions involving an
ending ACK, are changed by the SIE to a corresponding mode
which NAKs subsequent packets following the ACK. Exceptions
are modes 1010 and 1110
.
endpoint in which an ACK is transferred. These registers are
only unlocked by a CPU read of the register, which should be
done by the firmware only after the transaction is complete.
This represents about a 1-s window in which the CPU is
locked from register writes to these USB registers. Normally
the firmware should perform a register read at the beginning
of the Endpoint ISRs to unlock and get the mode register infor-
mation. The interlock on the Mode and Count registers
ensures that the firmware recognizes the changes that the
SIE might have made during the previous transaction. Note
that the setup bit of the mode register is NOT locked. This
means that before writing to the mode register, firmware must
first read the register to make sure that the setup bit is not set
(which indicates a setup was received, while processing the
current USB request). This read will of course unlock the
register. So care must be taken not to overwrite the register
elsewhere.
from the host
(Bit[7..5], Figure 17-2)
Setup
PID Status Bits
In
Out
ACK
Acknowledge phase completed
3
Changed by the SIE
2 1 0 Response
Endpoint Mode bits
CY7C65113C
SIE’s Response
to the Host
Page 36 of 48
Interrupt
Int
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