CYII5SC1300AA-QDC Cypress Semiconductor Corp, CYII5SC1300AA-QDC Datasheet - Page 15

• Manufacturer Part Number: CYII5SC1300AA-QDC
• Description: IC SENSOR IMMAGE COLOR 84-LCC
• Manufacturer: Cypress Semiconductor Corp
• Type: CMOS Imagingr

Specifications of CYII5SC1300AA-QDC

• Pixel Size: 6.7µm x 6.7µm
• Active Pixel Array: 1280H x 1024V
• Frames Per Second: 27
• Voltage - Supply: 3 V ~ 4.5 V
• Package / Case: 84-LCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

3.4 Image core operation
This section describes the functional operation of the image core signalling and supplies
considerations.
3.4.1 Image core operation and signalling
Figure 7 is a functional representation of the image core without sub-sampling and
column/row swapping circuits. Most of the involved signals are not available from the
outside because they are generated by the X-sequencer and SS-sequencer blocks.
The integration of the pixels is controlled by internal signals such as reset, sample, hold
are generated by the on-chip SS-sequencer that is controlled with the external signals
S
together with a Y_
calibrate the output amplifiers (during the row blanking time); signals necessary to do this
calibration are generated by the on-chip X-sequencer. This calibration sequence takes
typically 3.5 us and is necessary to remove Fixed Pattern Noise of the pixels and of the
column amplifiers themselves by means of a Double Sampling technique. After the row
blanking time the pixels are fed to the output amplifier. The pixel rate is equal to the
S
_
VDDR_LEFT
START
Contact
Cypress Semiconductor Corporation
IBIS5-A-1300
SYS_CLOCK
Datasheet
Y_CLOCK
Y_START
VDDH
[e-mail]
and S
Y-left addressing
S
_
BUS_A
BUS_B
CLOCK
STOP
Read-pointer
.
signal; internally this is followed by a calibration sequence to
Reading out the pixel array starts by applying a Y_
Pixel column
Document #: 38-05710 Rev.**(Revision 1.3)
3901 North First Street
Figure 7: Image core
Pixel
X addressing
A
SAMPLE
RESET
HOLD
Pixel
B
Pixel row
Column amplifiers
San Jose, CA 95134
Output amplifier
Y-right addressing
Page 15 of 67
Y_START
Y_CLOCK
PXL_OUT
Vddreset
VDDR_RIGHT
VDDC
408-943-2600
START