CYII5SC1300AA-QDC Cypress Semiconductor Corp, CYII5SC1300AA-QDC Datasheet - Page 20

• Manufacturer Part Number: CYII5SC1300AA-QDC
• Description: IC SENSOR IMMAGE COLOR 84-LCC
• Manufacturer: Cypress Semiconductor Corp
• Type: CMOS Imagingr

Specifications of CYII5SC1300AA-QDC

• Pixel Size: 6.7µm x 6.7µm
• Active Pixel Array: 1280H x 1024V
• Frames Per Second: 27
• Voltage - Supply: 3 V ~ 4.5 V
• Package / Case: 84-LCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

3.5 X-addressing
Because of the high pixel rate, the X-shift register selects 2 columns at the time for
readout, so it runs at half the system clock speed. All even columns are connected to bus
A; all odd columns to bus B. In the output amplifier, bus A and bus B are combined into
one stream of pixel data at system clock speed.
At the end of the row blanking time, the X
are open and the decoder output is fed to the register. The decoder loads a logical one in
one of the registers and a logical zero in the rest. This defines the starting point of the
window in the X direction. As soon as the X
shifting from the start position.
When no sub-sampling is required, X
moves 1 bit at the time. When sub-sampling is enabled, X
register moves 2 bits at the time. Taking into account that every register selects 2
columns, hence 2 pixels, sub-sampling results in the pattern “XXOOXXOO” when 8
pixels are considered.
Contact
Cypress Semiconductor Corporation
IBIS5-A-1300
Datasheet
SYS_CLOCK
[e-mail]
X_SYNC
X_SUB
X_SWAP30
X_SWAP12
BUS_A
BUS_B
1/2
Document #: 38-05710 Rev.**(Revision 1.3)
Reg(n)
A
Figure 8: Column structure
3901 North First Street
COL(i)
B
_SUB
DEC(n+1)
_SYNC
Reg(n+1)
is inactive. The pointer in the shift-register
COL(i+1)
_SYNC
A
switch is closed while all other switches
COL(i+2)
B
signal is released, the register starts
DEC(n+2)
San Jose, CA 95134
Reg(n+2)
COL(i+3)
_SUB
A
B
is activated. The shift
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Column
amplifiers
Output
amplifier
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