CYII5SC1300AA-QDC Cypress Semiconductor Corp, CYII5SC1300AA-QDC Datasheet - Page 39

• Manufacturer Part Number: CYII5SC1300AA-QDC
• Description: IC SENSOR IMMAGE COLOR 84-LCC
• Manufacturer: Cypress Semiconductor Corp
• Type: CMOS Imagingr

Specifications of CYII5SC1300AA-QDC

• Pixel Size: 6.7µm x 6.7µm
• Active Pixel Array: 1280H x 1024V
• Frames Per Second: 27
• Voltage - Supply: 3 V ~ 4.5 V
• Package / Case: 84-LCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

(I
register set at 9) but grey shadings if the sensor is saturated. See also paragraph 3.8.10 for
detailed ADC timing.
Bits 7:2 of the I
4:2) and in the Y-direction (bits 7:5). The sub-sampling modes and corresponding bit
setting are given in Table 12 (section 3.5) and Table 13 (section 3.6).
3.10.2.8 Amplifier register (6:0)
3.10.2.8.1 G
The gain bits determine the gain setting of the output amplifier. They are only effective if
U
3.10.2.8.2 U
In case U
unity feedback.
3.10.2.8.3 D
If D
from the two busses are multiplexed to output P
A
3.10.2.8.4 S
If STANDBY = 0, the complete output amplifier is put in standby. For normal use
S
3.10.2.9 DAC_RAW register (6:0) and DAC_FINE (6:0) register
These registers determine the black reference level at the output of the output amplifier.
Bit setting 1111111 for D
0000000 for D
paths have no offset mismatch, the D
from this value can be used to compensate the internal mismatch (see 3.7).
3.10.2.10
3.10.2.10.1 T
In case T
normal operation mode.
3.10.2.10.2 G
If G
TANDBY
MAGE
NITY
DC_IN
UAL_OUT
Contact
AMMA
Cypress Semiconductor Corporation
IBIS5-A-1300
= 0. The gains and corresponding bit setting are given in Table 14 section 3.7.2).
_
Datasheet
. The gain amplifier and output driver of the second path are put in standby.
CORE
RISTATE
NITY
should be set to 1.
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TANDBY
RISTATE_OUT
AIN
NITY
UAL_OUT
AMMA
is set to 1, the ADC input to output conversion is linear; otherwise the
register set at 1 or 2) or black-black-white-white-black-black (I
AC
ADC register (2:0)
= 1, the two output amplifiers are active. If D
= 1, the gain setting of G
MAGE
(bits 3:0)
(bit 4)
_
= 0, the ADC_D<9:0> outputs are in tri-state mode. T
RAW
(bit 1)
_
(bit 5)
CORE
register gives the lowest offset voltage. Ideally, if the two output
(bit 0)
AC
register define the sub-sampling mode in the X-direction (bits
Document #: 38-05710 Rev.**(Revision 1.3)
_
RAW
3901 North First Street
register gives the highest offset voltage, bit setting
AC
_
AIN
FINE
is bypassed and the gain amplifier is put in
register must be set to 1000000. Deviation
XL_OUT1
San Jose, CA 95134
which should be connected to
UAL_OUT
Page 39 of 67
= 0, the signals
RISTATE
408-943-2600
MAGE
= 1 for
_
CORE