CYII5SC1300AA-QDC Cypress Semiconductor Corp, CYII5SC1300AA-QDC Datasheet - Page 36

• Manufacturer Part Number: CYII5SC1300AA-QDC
• Description: IC SENSOR IMMAGE COLOR 84-LCC
• Manufacturer: Cypress Semiconductor Corp
• Type: CMOS Imagingr

Specifications of CYII5SC1300AA-QDC

• Pixel Size: 6.7µm x 6.7µm
• Active Pixel Array: 1280H x 1024V
• Frames Per Second: 27
• Voltage - Supply: 3 V ~ 4.5 V
• Package / Case: 84-LCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

that the longest SS granularity is used (bits 6&7 set to ‘1’).
The clock that drives the X-sequencer can be a multiple of 4, 8, 16 or 32 times the system
clock. Clocking the X-sequencer at a slower rate (longer row blanking time; pixel read
out speed is always equal to the S
same light conditions.
3.10.2.1.5 Pixel reset knee-point for multiple slope operation (bits 8, 9 and 10)
In normal (single slope) mode the pixel reset is controlled from the left side of the image
core using the voltage applied on pin V
In multiple slope operation one or more variable pixel reset voltages have to be applied.
Bits K
voltage.
Bit K
the pixel reset voltage (V
Bit K
synchronous shutter mode. In rolling shutter mode, only the bits K
must be used to select the second knee-point in dual slope operation.
The actual knee-point depends on V
Contact
Cypress Semiconductor Corporation
GRAN_SS_SEQ_MSB/LSB
IBIS5-A-1300
NEE_POINT_ENABLE
GRAN_X_SEQ_MSB/LSB
NEE_POINT_ENABLE
NEE_POINT_MSB
* using a SYS_CLOCK of 40 MHz (25 ns period)
* using a SYS_CLOCK of 40 MHz (25 ns period)
Datasheet
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MSB/LSB
00
01
10
11
00
01
10
11
KNEE_POINT
00
01
10
11
and K
DDR
ENABLE (1)
set to “1” switches control to the right side of the image core so
Table 19: SS sequencer clock granularities
Table 20: X sequencer clock granularities
Table 21: Multiple slope register settings
should only be used for multiple slope operation in
_
0 or 1
Document #: 38-05710 Rev.**(Revision 1.3)
RIGHT
NEE_POINT_LSB
1
1
1
YSTEM_CLOCK
3901 North First Street
DDH
), selected by bits K
SS-sequencer clock
128 x SYS_CLOCK
256 x SYS_CLOCK
X-sequencer clock
32 x SYS_CLOCK
64 x SYS_CLOCK
16 x SYS_CLOCK
32 x SYS_CLOCK
DDR_LEFT
4 x SYS_CLOCK
8 x SYS_CLOCK
, V
VDDR_LEFT
VDDR_LEFT – 0.76
VDDR_LEFT – 1.52
VDDR_LEFT – 2.28
Pixel reset voltage (V)
DDR_LEFT
VDDR_RIGHT
select the on chip-generated pixel reset
) can result in more signal swing for the
as pixel reset voltage.
and V
NEE_POINT_MSB/LSB
San Jose, CA 95134
DDC
Row Blanking Time*
Integration time step*
applied to the sensor.
Knee-point
+ 0.76
+ 1.52
+ 2.28
Page 36 of 67
NEE_POINT_MSB/LSB
3.5 us
14 us
28 us
800 ns
7 us
1.6 us
3.2 us
6.4 us
(V)
0
408-943-2600
, is used.