CYII5SC1300AA-QDC Cypress Semiconductor Corp, CYII5SC1300AA-QDC Datasheet - Page 24

• Manufacturer Part Number: CYII5SC1300AA-QDC
• Description: IC SENSOR IMMAGE COLOR 84-LCC
• Manufacturer: Cypress Semiconductor Corp
• Type: CMOS Imagingr

Specifications of CYII5SC1300AA-QDC

• Pixel Size: 6.7µm x 6.7µm
• Active Pixel Array: 1280H x 1024V
• Frames Per Second: 27
• Voltage - Supply: 3 V ~ 4.5 V
• Package / Case: 84-LCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

FPN corrected pixel value. This pixel value is fed to the first amplifier stage which has an
adjustable gain, controlled by a 4-bit word (“GAIN [0…3]”).
After this, a unity feedback amplifier buffers the signal and the signal leaves the chip.
This 2
slew rate of the output signal. The whole amplifier chain is designed for a data rate of 40
Mpix/s (@20 pF).
3.7.2 Output amplifier gain control
The output amplifier gain is controlled by a 4-bit word set in the A
section 3.10.2.8). An overview of the gain settings is given in Table 14.
3.7.3 Setting of the DAC reference voltages
In the output amplifier, the offset can be trimmed by loading registers D
D
D
These registers are inputs for 2 DACs (see Figure 10) that operate on the same resistor
that is connected between pins D
defined using a resistive division with R
ACFINE_REG
AC_FINE
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IBIS5-A-1300
nd
Datasheet
amplifier stage determines the maximal readout speed, i.e. the bandwidth and the
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is used to tune the offset between the even and odd columns.
.
D
0000
0001
0010
0011
0100
0101
0110
0111
AC_RAW
bits
is used to adjust the offset of the output amplifier and
Document #: 38-05710 Rev.**(Revision 1.3)
Table 14: Overview gain settings
DC gain
1.37
1.62
1.96
2.33
2.76
3.50
4.25
5.20
AC_VHIGH
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VHIGH
, R
and D
1000
1001
1010
1011
1100
1101
1110
1111
bits
DAC
AC_VLOW
and R
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VLOW
DC gain
11.00
11.37
11.84
12.32
12.42
6.25
7.89
9.21
. The range of the DAC is
.
MPLIFIER
Page 24 of 67
ACRAW_REG
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register (see
and