QT2032-EKG-1A2 Applied Micro Circuits Corporation, QT2032-EKG-1A2 Datasheet - Page 100

• Manufacturer Part Number: QT2032-EKG-1A2
• Manufacturer: Applied Micro Circuits Corporation

Specifications of QT2032-EKG-1A2

• Lead Free Status / RoHS Status: Supplier Unconfirmed

QT2022/32 - Data Sheet: DS3051
11.4 Serial Interface Test Features
11.4.1 PRBS31 Test Pattern Generator
A pseudo-random pattern generator feature is available to test the 10 Gb/s serial transmitter. When the PRBS31
31
pattern generator is enabled by setting MDIO bit 3.42.4 (3.2Ah.4), a 2
-1 pseudorandom pattern is output at
28
31
TXOUT. The polynomial -(1+x
+x
) is used to generate the pattern. This polynomial produces the same output
as the IEEE standard algorithm shown in Figure 39 (see IEEE 802.3-2005 Clause 49.2.8). The initial seed of this
algorithm will not be all zeros.
Note that the PRBS31 output pattern is inverted from the standard pattern generated by most test equipment. To
invert the pattern from the QT2022/32, set the TXOUT_SEL pin high. Alternatively, configure the test equipment to
accept the inverted pattern.
In the QT2032 product, this generator is available in both LAN and WAN operation. It is controlled by a different bit
depending on the mode. The control and counter registers are listed in Table 42 on page 101.
If both the jitter test pattern and the PRBS31 test pattern are enabled, the PRBS31 mode will be chosen (LAN
mode).
Figure 39: PRBS31 Pattern Generator
S0
S1
S2
S27
S30
S28
S29
PRBS31 Pattern Output
11.4.2 PRBS31 Test Pattern Checker
A pseudo-random pattern error counter feature is available to test the 10 Gb/s serial receiver. When the PRBS31
31
error detector is enabled a 2
-1 PRBS pattern is expected on the receive path input. The PRBS31 pattern checker
is self-synchronizing and produces the same result as the IEEE standard algorithm shown in Figure 40 (see IEEE
802.3-2005 Clause 49.2.12). Pattern errors are counted by an 16-bit counter and can be observed at MDIO regis-
ter 3.43 (3.2Bh), which is a non-rollover counter that is cleared on read. When an isolated bit error occurs, it will
cause the PRBS31 pattern error output to go high 3 times, once when it is received and once when it is at each tap.
Thus, each isolated error will be counted 3 times in the counter.
Note that the expected PRBS31 pattern is inverted from the standard pattern generated by most test equipment. To
invert the input to the QT2022/32, set the RXIN_SEL pin high (or set MDIO register bit 1.D003h.4 to 1 to invert the
RXIN_SEL pad polarity). Alternatively, configure the test equipment to transmit the inverted pattern. The built-in
pattern checker is compatible with the built-in generator with no inversion applied to either pattern.
In the QT2032, this counter is available in both LAN and WAN operation. It is controlled by a different bit depending
on the mode. The same 16-bit counter register is used in both modes. The control and counter registers are listed
in Table 42 on page 101.
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