QT2032-EKG-1A2 Applied Micro Circuits Corporation, QT2032-EKG-1A2 Datasheet - Page 17

• Manufacturer Part Number: QT2032-EKG-1A2
• Manufacturer: Applied Micro Circuits Corporation

Specifications of QT2032-EKG-1A2

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Table 3:
Revision 5.11
C3
E2
E1
C1
B1
A1
C11
D6
D3
G3
E7
CMOS Outputs (note: all CMOS outputs are 3.3V tolerant open drain)
E12
E10
E11
Ball
TXFAULT
(XFPMODNR)
PRTAD<0>
PRTAD<1>
PRTAD<2>
PRTAD<3>
PRTAD<4>
RESETN
TDI
TCK
TRST_N
TMS
LTIMEOK
RDCC
RDCC_CLK
Signal Name
QT2022/32 Ball Assignment & Signal Description (Continued)
I
I
I
I
I
I
I
O
O
O
Dir.
AppliedMicro - Confidential & Proprietary
CMOS with 50kΩ
pullup to 1.2V
CMOS
no pullup or pulldown
CMOS with
hysteresis
25kΩ pullup
CMOS
36kΩ pullup
(no pullup/dn)
25kΩ pullup
36kΩ pullup
CMOS open drain
(see note1)
CMOS open drain
(see note1)
CMOS open drain
(see note1)
Type
With XFP=0, External laser or laser-driver fault indicator as per XENPAK
MSA
logic low = normal operation
logic high = fault condition
(See “Laser Driver Enable Pin (TXENABLE)” on page 69.)
With XFP=1, high level indicates XFP module not ready
Port address for MDIO transactions. See “Management Frame Format” on
page 74. for more information on the MDIO/C interface.
reset, active low
logic low = reset condition
logic high = normal operation
Note: the TAP port controller is only reset by the TRST_N pin and is
unaffected by RESETN
Note: in a module application XFP=0 & the external cap for the powerup
reset must be connected to the TRST_N input. For further details, please
see Section 18.5 on page 210
Test pins for Test Access Port (or internal scan testing when SCAN
instruction written to TAP).
Test data input (scan in)
Test clock input (scan clock)
Test reset, active low (hold high for scan)
Test mode select, active low (hold high for scan)
QT2032:
Line-timing internal enable indication.
logic high = conditions are valid for line-timing operation and it is internally
enabled.
A low level can be used to center the external VXCO in a VXCO-only
application.
(see Section 6.2.4, “VCXO PLL,” on page 32 for a description of the logic)
QT2022:
Unused. Connect to GND.
QT2032:
Receive data communication channel output for both section and line
SONET overhead data; timed from the RDCC_CLK clock output. Please
see Section 7.3.8, “Transport Overhead Serial Interface,” on page 48.
QT2022:
Unused. Connect to GND.
QT2032:
Gapped clock used for timing RDCC output.
Please see Section 7.3.8, “Transport Overhead Serial Interface,” on
page 48.
QT2022:
Unused. Connect to GND.
with XFP=0, also resets the core and is to be used as the connection
point for an external cap to GND for a powerup reset.
Description
QT2022/32 - Data Sheet: DS3051
17