QT2032-EKG-1A2 Applied Micro Circuits Corporation, QT2032-EKG-1A2 Datasheet - Page 102

• Manufacturer Part Number: QT2032-EKG-1A2
• Manufacturer: Applied Micro Circuits Corporation

Specifications of QT2032-EKG-1A2

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QT2022/32 - Data Sheet: DS3051
11.4.3 Timed BER Test
A BER test can be performed on the RXIN receive signal. The 2 31 -1 PRBS test pattern checker is used to count
detected errors within a specified time period. The time period in seconds is set by the value in MDIO register
3.C001h. The errors are reported in the MDIO test pattern error counter register, 3.34. Once the PRBS test pattern
checker has been enabled, the BER test is enabled by writing a 1 to MDIO register 3.C000h.12. The ’BER in prog-
ress’ bit, MDIO 3.C000h.14, will be 1 while the BER test is in progress. The completion of the BER test is indicated
by the ‘BER DONE’ bit, 3.C000h.15, going high. At this point the error count can be read from register 3.34. The
error count should not be read until the completion of the BER test, as this will clear the error counter and give
incorrect results.
Table 43: BER Test Procedure
11.4.4 AMCC Fiber Test Pattern Generator
The fiber output can be configured to transmit a user-defined 16 bit code word or, alternatively, a static output (no
transitions). The 16-bit user defined test pattern is set in MDIO register 1.C031. When enabled, the programmed
pattern will be continuously transmitted on the TXOUT output.
Transmission of the test pattern is enabled by setting MDIO register bit 1.C030h.0 to 1. The desired pattern is
selected by setting MDIO register bit 1.C030h.1, where a 1 selects the user-defined pattern and a 0 selects the
static output.
11.5 WIS Test Features (QT2032 only)
The WIS implements three serial test patterns for testing the PMA and PMD layers. These include a square wave
test pattern, an unframed PRBS31 pattern, and a framed mixed frequency test pattern. These patterns are imple-
mented in accordance with IEEE 802.3 Clause 50.3.8. The PRBS31 pattern generator and checker are described
in Section 11.4.
102
Step #
1
2
3
4
5
6
3..6
Step
Write 1 to MDIO 3.42.5 in LAN mode (2.7.5 in WAN mode - QT2032 only)
This enables the PRBS 2
Write desired length of BER test in seconds to 3.C001h.15:0
write 1 to 3.C000h.12
(this register bit must have been 0 previously)
This clears the error count and starts the BER test running
Check the BER in progress flag, 3.C000h.14 to see when it changes from1 to 0 to indicate the BER test is complete
OR
Check the BER test complete flag, 3.C000h.15 to see when it is 1
Read the error count register, (3.43 in LAN mode, 2.9 in WAN mode)
Write a 0 to MDIO 3.C00h.12 to disable the BER test
Repeat steps 3 to 6 for multiple BER tests
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31
-1 receive test pattern checker
Revision 5.11