QT2032-EKG-1A2 Applied Micro Circuits Corporation, QT2032-EKG-1A2 Datasheet - Page 16

• Manufacturer Part Number: QT2032-EKG-1A2
• Manufacturer: Applied Micro Circuits Corporation

Specifications of QT2032-EKG-1A2

• Lead Free Status / RoHS Status: Supplier Unconfirmed

QT2022/32 - Data Sheet: DS3051
Table 3:
16
C6
C2
C13
C5
C7
D12
C10
E8
C8
F4
C4
E3
Ball
PHOFF_EN
LEGACY
RXIN_SEL
TxXAUI_SEL
(SCAN_EN)
RxXAUI_SEL
RXLOSB_I
(XFPRXLOS)
XFP
EQ_EN
EEPROM_PROT
(XFPMODABS)
MDC
TXOUT_SEL
LASI_INTB
(XFPINTB)
Signal Name
QT2022/32 Ball Assignment & Signal Description (Continued)
I
I
I
I
I
I
I
I
I
I
I
I
Dir.
AppliedMicro - Confidential & Proprietary
CMOS with 50kΩ
pulldown
CMOS with 50kΩ
pulldown
CMOS with 50kΩ
pulldown
CMOS with 50kΩ
pulldown
CMOS with 50kΩ
pulldown
CMOS with 50kΩ
pullup to 1.2V
CMOS with 50kΩ
pulldown
CMOS with 50kΩ
pulldown
CMOS with 50kΩ
pullup to 1.2V
CMOS
CMOS with 50kΩ
pulldown
CMOS with 50kΩ
pullup to 1.2V
Type
Phase Offset Enable pin (NEW).
Enables adjustment of Receive CDR decision phase from nominal. Used in
conjunction with the PHASE_OFFSET pin. For test purposes only.
0 = phase offset control disabled (default)
1 = phase offset control enabled.
0 (default) = new register map definitions
1=reverts to 2021 register map definitions (see LEGACY mode description)
Polarity control for RXI, 50 kΩ pulldown
RXIN_SEL=0 default polarity
RXIN_SEL=1 inverted polarity
XAUI Transmit path lane order control, 50 kΩ pulldown
0 = default lane ordering
1 = inverted lane ordering
Enable scan in scan mode
XAUI receive path lane order control, 50 kΩ pulldown
0 = default lane ordering
1 = inverted lane ordering
Receive optical signal loss indicator input (can be driven directly by
LOSOUTB or by an external source)
When XFP=0, active low indicates RX signal loss
with XFP=1, active high indicates RX signal loss
(See Section 8.2.2 on page 54)
XFP application mode select;
0 = non-XFP application, default; high-sensitivity input selected on 10Gb/s
input
1 = XFP application; equalization option selected on 10Gb/s input (can be
over-ridden via MDIO register bit 1.C030h.6 - ‘override_xfp_eqn’). Also
changes function of TXPLLOUT, LOSOUTB, TXFAULT, TXON,
TXENABLE, EEPROM_PROT, RXLOSB_I and TRST_N.
Receive Equalizer Enable pin (NEW).
Allows receive equalizer to be enabled.
0 = equalizer state determined by XFP pin (default)
1 = equalizer on.
With XFP=0, EEPROM interface write protection pin; Scan enable when in
scan mode
1 (default) = no writes to protected EEPROM registers allowed;
With XFP=1, high level indicates XFP module absent
MDIO interface clock
TXOUT polarity control, 50 kΩ pulldown
0 = default polarity
1 = inverted polarity
With XFP=0, Active low interrupt input to LASI; (See Section 8.2.12 on
page 57).
With XFP=1, active low interrupt input indicating XFP module fault
condition.
Description
Revision 5.11