QT2032-EKG-1A2 Applied Micro Circuits Corporation, QT2032-EKG-1A2 Datasheet - Page 32

• Manufacturer Part Number: QT2032-EKG-1A2
• Manufacturer: Applied Micro Circuits Corporation

Specifications of QT2032-EKG-1A2

• Lead Free Status / RoHS Status: Supplier Unconfirmed

QT2022/32 - Data Sheet: DS3051
6.2.3 Forced Line Timing Mode
The Forced Line Timing mode forces the TX Fiber Output to derive timing from the RX Fiber Input recovered clock.
The Forced Line Timing mode is useful for various test scenarios or implementations where the timing is controlled
externally. This mode is supported in WAN and LAN modes.
Support for External Line Timing Control
In order to support external control (e.g., by firmware) of the line timing the LASI may be configured to interrupt on
any of the relevant receiver conditions. Refer to Section 8.4.1 on page 62. Relevant defects and conditions include:
A separate interrupt enable bit for each of the conditions listed above is provided. By default, each enable bit is
clear. The enable bit for each condition may be set as required by the implementation.
6.2.4 VCXO PLL
As discussed in Section 6.2.1 on page 27, the QT2032 provides support for a VCXO based PLL to filter phase
noise on the SREFCLK or recovered clock to ensure compliant jitter generation and jitter transfer performance as
measured on the TX Fiber Output. The VCXO PLL is supported only in WAN mode. The QT2032 further supports
a self-centering VCXO to reduce board cost by eliminating the need for a fixed frequency XO driving SREFCLK
when the VXCO PLL is used.
The QT2032 VCXO PLL interface is illustrated in Figure 9.
When using the VCXO PLL, VCXOB is set low, and the VCXO drives the reference input of the TX PLL. The on-
chip VCXO phase-frequency detector (VCXO PFD) compares the phase and frequency of the VCXO clock with
that of a reference clock and generates a tri-state output which drives an external opamp configured as a differen-
tial integrator. The external opamp and power supply are chosen to provide the appropriate voltage swing for the
VCXO. The reference clock input to the VCXO PFD may be from either SREFCLK or the RX Fiber Input recovered
clock (rx_fiber_clock). The selectable divide-by-4 blocks at the VCXO PFD inputs allow for any combination of 155
MHz or 622 MHz reference clock and VCXO frequencies based on the settings of REFSEL622 and VCXOSEL622.
For implementation details refer to Section 6.2.5 on page 34.
The LTIMEOK output indicates that line timing conditions are valid and that line timing is internally enabled. In a
linetiming application with no reference applied to SREFCLK, indicated by pulling VCXOONLY high, the LTIMEOK
output being low may be used to force the VCXO to its center frequency; when the LTIMEOK output is low, the
VCXO PFD differential output is coincidentally forced to 0 V. The logic which generates LTIMEOK is illustrated in
figure 8 on page 31.
QT2032 VCXO interface parameters are specified in Table 74 on page 202.
32
VCXO PLL Interface
1. PMA LOS defect RXLOSB_I = 0 (visible in MDIO 1.10d.0). This condition assumes that XFP = 0. If XFP = 1
2. PMA sync_err defect (MDIO register 1.C001h.1)
3. WIS LOF defect (MDIO register 2.33d.7)
4. WIS Line AIS defect (MDIO register 2.33d.4)
5. Validated Synchronization Status message in received WIS S1 byte has changed. Refer to section
then the RXLOSB_I active state is inverted.
Section 7.3.3 on page 47.
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