QT2032-EKG-1A2 Applied Micro Circuits Corporation, QT2032-EKG-1A2 Datasheet - Page 47

• Manufacturer Part Number: QT2032-EKG-1A2
• Manufacturer: Applied Micro Circuits Corporation

Specifications of QT2032-EKG-1A2

• Lead Free Status / RoHS Status: Supplier Unconfirmed

QT2022/32 - Data Sheet: DS3051
7.3.1 SS Bits (H1)
The SS bits in the STS-1 #1 transmit overhead can be programmed by the user. The SS bits are located in bits 5
and 6 of the H1 octet in the SONET overhead. This feature allows the QT2032 transmitted frame to be compatible
with SDH networks, where the SS bits are typically set to ‘10’. For SONET networks, the default value of ‘00’
should be used. To change the SS bit value, enter the required value in MDIO register field 2.C001h.7:6. To enable
insertion of the new SS bits, set 2.C002h.9 to ‘1’.
In the 191 subsequent STS-1 fields of the transmit overhead, the SS bits are set to ‘00’.
The QT2032’s WIS receive processor ignores the SS bits in the STS-1 #1 overhead field. For STS-1 #2-192, a
value of ‘00’ is expected.
7.3.2 APS Channel (K1 and K2)
The APS bytes are located in the first STS-1 of the STS-192 only and are used for automatic protection switching
signaling.
A new value in either byte is only validated after it has been received in 3 consecutive frames. Upon validation of a
new K1 or K2 byte, the respective K byte is stored in a status register and an interrupt is generated (the interrupt
can be masked). The validation of the K bytes is not affected by any alarm or defect.
If 3 identical consecutive K bytes are not found in 12 frames, an inconsistent K byte interrupt is generated (the
interrupt can be masked).
A programmable value for K1 and K2 can be transmitted by QT2032 if the feature is enabled (vendor specific reg-
ister 2.C002h). For the K2 byte only the 5 MSB bits can be programmed. The 3 LSB bits are reserved for RDI-L
1
alarm transmission.
7.3.3 Synchronization Status (S1)
The synchronization status byte is located in the first STS-1 of the STS-192 only, and is used to convey the syn-
chronization status of the network element.
A new value is only validated after it has been received in 8 consecutive frames. Upon validation of a new S1 byte,
the S1 byte is stored in a status register and an interrupt is generated (the interrupt can be masked).
A programmable value for S1 can be transmitted by QT2032 if the feature is enabled (vendor specific register
2.C002h).
7.3.4 Line BIP-8 Signal Fail (SF)
QT2032 generates a Signal Failure (SF) alarm if the number of Line BIP-8 (B2) errors monitored during a program-
mable timing window (2.C410h) exceeds a programmable threshold (2.C411h). There is a second programmable
threshold (2.C412h) which is used to provide hysteresis when removing the SF alarm. The user must specify the
correct thresholds and timing window to achieve the desired BER monitoring. SF coding violations over the timing
window are reported in 2.C413h, a 16 bit non-rollover counter.
At the end of each timing window, a time-out alarm is generated to notify the user that the timing window has
ended. The number of coding violations is latched to 2.C413h at the end of each window. The time-out alarm can
be programmed to trip the LASI interrupt by enabling the ‘SF Timing Window Expired Flag’ in the WIS Extended
Alarm register (MDIO register bit 2.C502h.11). The LASI interrupt can then be used by system firmware to trigger
periodic polling of the chip in order to monitor the SF error rate.
SF monitoring is enabled by setting MDIO register bit 2.C002h.8 to 1.
1. In SONET, bit 8 is the LSB and bit 1 is the MSB.
Revision 5.11
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