QT2032-EKG-1A2 Applied Micro Circuits Corporation, QT2032-EKG-1A2 Datasheet - Page 13

• Manufacturer Part Number: QT2032-EKG-1A2
• Manufacturer: Applied Micro Circuits Corporation

Specifications of QT2032-EKG-1A2

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Table 3:
Revision 5.11
CML Outputs
N6
N7
D14
D13
A14
B14
A12
B12
A10
B10
G13
G14
P1
P2
H1
H2
CML Inputs
F1
F2
M1
M2
Ball
TXOUTP
TXOUTN
RxXAUI0P
RxXAUI0N
RxXAUI1P
RxXAUI1N
RxXAUI2P
RxXAUI2N
RxXAUI3P
RxXAUI3N
RXPLLOUTP
RXPLLOUTN
TXPLLOUTP
TXPLLOUTN
(REFCLK2P,
REFCLK2N)
VCXOCTLP
VCXOCTLN
EREFCLKP
EREFCLKN
SREFCLKP
SREFCLKN
Signal Name
QT2022/32 Ball Assignment & Signal Description
O
O
O
O
O
O
O/I
O
I
I
Dir.
AppliedMicro - Confidential & Proprietary
CML
CML
CML
CML
CML
CML
CML
CML
CML
CML
Type
9.95 - 10.5 Gb/s transmit differential voltage outputs.
100 Ω differential impedance.
3.125 Gb/s differential output data from QT2022/32 to XAUI interface - lane
0
3.125 Gb/s differential output data from QT2022/32 to XAUI interface - lane
1
3.125 Gb/s differential output data from QT2022/32 to XAUI interface - lane
2
3.125 Gb/s differential output data from QT2022/32 to XAUI interface - lane
3
Clock output from receive input data PLL
Used for monitoring only. Leave unconnected.
Configurable as either a differential transmit clock driver (default) or as a
reference clock input instead of EREFCLK (with MDIO bit 1.C001h.7=1).
The output clock frequency is controlled by MDIObit 1.C001h.2. The default
frequencies are:
With XFP=1: divide-by-64, can be used as reference clock to the XFP
module; 161.13 MHz (10GE) or 164.355 MHz (10GFC)
With XFP=0: divide-by-66; 156.25MHz (10GE) or 159.375 (10GFC)
Enabling the driver circuitry is controlled by MDIO bit 1.C001h.3. By default:
With XFP=1, the driver is enabled
With XFP=0, the driver is disabled
Note: for the case where the pin is configured as a reference clock input, the
driver circuitry is disabled.
QT2032:
Output of phase-frequency detector which drives the external loop filter as
part of the VCXO control.
QT2022:
Unused. Leave unconnected.
LAN reference clock input for fiber-side TXPLL.
156.25 MHz (10GE) or 159.375 (10GFC)
On chip 50Ω terminations to 1.2 V. Requires external AC coupling.
QT2032:
SONET reference clock input for fiber-side TXPLL in WAN-mode
155.52 MHz or 622.08 MHz selected by REFSEL622 pin;
AC coupled with on chip 50Ω terminations to 1.2 V
QT2022:
Unused. Leave unconnected.
Description
QT2022/32 - Data Sheet: DS3051
13