UJA1066TW/5V0,518 NXP Semiconductors, UJA1066TW/5V0,518 Datasheet
UJA1066TW/5V0,518
Specifications of UJA1066TW/5V0,518
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UJA1066TW/5V0,518 Summary of contents
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... General description The UJA1066 fail-safe System Basis Chip (SBC) replaces basic discrete components which are common in every Electronic Control Unit (ECU) with a Controller Area Network (CAN) interface. The fail-safe SBC supports all networking applications that control various power and sensor peripherals by using high-speed CAN as the main network interface. The fail-safe SBC contains the following integrated devices: • ...
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... NXP Semiconductors 2. Features and benefits 2.1 General Contains a full set of CAN ECU functions: CAN transceiver Voltage regulator for the microcontroller (3 5.0 V) Separate voltage regulator for the CAN transceiver (5 V) Enhanced window watchdog with on-chip oscillator Serial Peripheral Interface (SPI) for the microcontroller ...
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... NXP Semiconductors 2.3 Power management Smart operating modes and power management modes Cyclic wake-up capability in Standby and Sleep modes Local wake-up input with cyclic supply feature Remote wake-up capability via the CAN-bus External voltage regulators can easily be incorporated into the power supply system ...
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... NXP Semiconductors 3. Ordering information Table 1. Ordering information [1] Type number Package Name UJA1066TW HTSSOP32 [1] UJA1066TW/5V0 is for the 5 V version; UJA1066TW/3V3 is for the 3.3 V version. 4. Block diagram 31 SENSE 32 BAT42 27 BAT14 29 SYSINH INH/LIMP 7 INTN 18 WAKE WAKE 16 TEST CHIP TEMPERATURE 11 SCK 9 SDI SPI 10 SDO 12 SCS ...
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... NXP Semiconductors 5. Pinning information 5.1 Pinning Fig 2. 5.2 Pin description Table 2. Symbol n.c. n.c. i.c. V1 i.c. RSTN INTN EN SDI SDO SCK SCS TXDC RXDC n.c. TEST UJA1066_2 Product data sheet n. TEST1 4 V1 TEST2 5 RSTN 6 INTN UJA1066TW 9 SDI SDO 10 SCK ...
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... NXP Semiconductors Table 2. Symbol INH/LIMP WAKE n.c. V2 CANH CANL GND SPLIT i.c. i.c. BAT14 n.c. SYSINH V3 SENSE BAT42 The exposed die pad at the bottom of the package allows better dissipation of heat from the SBC via the printed-circuit board. The exposed die pad is not connected to any active part of the IC and can be left floating, or can be connected to GND for the best EMC performance ...
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... NXP Semiconductors 6. Functional description 6.1 Introduction The UJA1066 combines all the peripheral functions found around a microcontroller in a typical automotive networking application in a single, dedicated chip. These functions are: • Power supply for the microcontroller • Power supply for the CAN transceiver • ...
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... NXP Semiconductors mode change via SPI watchdog trigger Normal mode V1: ON SYSINH: HIGH CAN: all modes available flash entry enabled (111/001/111 mode sequence) watchdog: window OR mode change to Sleep with pending wake-up INH/LIMP: HIGH/LOW/float EN: HIGH/LOW init Normal mode via SPI successful init Normal mode ...
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... NXP Semiconductors 6.2.1 Start-up mode Start-up mode is the ‘home page’ of the SBC. This mode is entered when battery and ground are connected for the first time. Start-up mode is also entered after any event that results in a system reset. The reset source information is provided by the SBC to support software initialization cycles that depend on the reset event ...
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... NXP Semiconductors Entering Normal mode does not activate the CAN transceiver automatically. The CAN Mode Control (CMC) bit must be set to activate the CAN medium if required, allowing local cyclic wake-up scenarios to be implemented without affecting the CAN-bus. 6.2.5 Standby mode In Standby mode, the system reduced current consumption state. Entering Standby mode overrides the CMC bit, allowing the CAN transceiver to enter the low-power mode autonomously ...
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... NXP Semiconductors • Cyclic wake-up by the watchdog via an interrupt signal to the microcontroller (the microcontroller is triggered periodically and checked for the correct response) • Cyclic wake-up by the watchdog via a reset signal (a reset is performed periodically; the SBC provides information about the reset source to allow different start sequences after reset) • ...
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... NXP Semiconductors Once in Start-up mode the application software has to write Operating Mode code 011 to the Mode register within t successfully received hardware reset (handshake between the SBC and the microcontroller fed back. The transition from Start-up mode to Flash mode can only occur once after the Flash entry sequence has been completed. ...
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... NXP Semiconductors The following corrupted watchdog accesses result in an immediate system reset: • Illegal watchdog period coding; only ten different codes are valid • Illegal operating mode coding; only six different codes are valid Any microcontroller-driven mode change is synchronized with a watchdog access by reading the mode information and the watchdog period information from the same register ...
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... NXP Semiconductors The watchdog window is defined to be between 50 % and 100 % of the nominal programmed watchdog period. Any ‘too early’ or ‘too late’ watchdog access or incorrect Mode register code access will result in an immediate system reset, when the SBC will revert to Start-up mode. ...
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... NXP Semiconductors If the microcontroller supply current rises above I watchdog will be restarted using the watchdog period last used and, if enabled, a watchdog restart interrupt will be generated. In the case of a direct mode change to Standby with watchdog OFF selected, the longest possible watchdog period is used. It should be noted that V1 current monitoring is not active in Sleep mode ...
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... NXP Semiconductors The behavior of pin RSTN is illustrated in setting of bit RLC (which defines the reset length). Once an external reset event has been detected, the system controller enters Start-up mode. The watchdog now starts to monitor pin RSTN as illustrated in enter Fail-safe mode (see V1 V RSTN Fig 6 ...
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... NXP Semiconductors Pin RSTN is monitored for a continuously clamped LOW condition. If the SBC pulls RSTN HIGH, but it remains LOW for longer than t mode since this indicates an application failure. The SBC also detects if pin RSTN is clamped HIGH. If the SBC pulls RSTN LOW, but it remains HIGH for longer than t mode since the microcontroller can no longer be reset ...
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... NXP Semiconductors A dedicated V1 supply comparator (V1 Monitor) monitors V1 for undervoltage events (V O(V1) of the lower V1 undervoltage reset thresholds has been selected (see Regulator V1 is overload protected. The maximum output current available at pin V1 depends on the voltage applied at pin BAT14 (see power dissipation should be taken into account for thermal reasons. ...
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... NXP Semiconductors 6.7 CAN transceiver The integrated high-speed CAN transceiver on the UJA1066 is an advanced ISO 11898-2 and ISO 11898-5 compliant transceiver. In addition to standard high-speed CAN transceiver features, the UJA1066 transceiver provides the following: • Enhanced error handling and reporting of bus and RXD/TXD failures; these failures are separately identified in the System Diagnosis register • ...
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... NXP Semiconductors Normal mode OR Flash mode AND CMC = 1 Normal mode OR Flash mode AND CMC = 0 AND CPNC = 0 On-line mode V2: ON/OFF (V2C/V2D) transmitter: OFF RXDC: wake-up (active LOW) SPLIT: ON/OFF (CSC/V2D) CPNC = 0 no activity for t > t CAN wake-up filter passed AND CPNC = 0 power-on Fig 8 ...
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... NXP Semiconductors 6.7.1.2 On-line mode In On-line mode the CAN-bus pins and pin SPLIT (if enabled) are biased to the normal levels. The CAN transmitter is deactivated and RXDC reflects the CAN wake-up status. A CAN wake-up event is signalled to the microcontroller by clearing RXDC. If the bus stays continuously dominant or recessive for the Off-line time (t Off-line state will be entered ...
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... NXP Semiconductors Fig 9. 6.7.3 Termination control In Active mode, On-line mode and On-line Listen mode, CANH and CANL are terminated to 0.5 × disabled due to an overload condition both pins become floating. 6.7.4 Bus, RXD and TXD failure detection The UJA1066 can distinguish between bus, RXD and TXD failures as indicated in All failures are signalled individually in the CANFD bits in the System Diagnosis register ...
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... NXP Semiconductors 6.7.4.3 GND shift detection The SBC can detect ground shifts in reference to the CAN-bus. Two different ground shift detection levels can be selected with the GSTHC bit in the Configuration register. The failure can be read out in the System Diagnosis register. Any detected or recovered GND shift event is signalled via a GSI an interrupt, if enabled ...
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... NXP Semiconductors continuously ON, the WAKE input will be sampled continuously, regardless of the level of bit WSC. The dedicated bits Edge Wake-up Status (EWS) and WAKE Level Status (WLS) in the System Status register reflect the actual status of pin WAKE. The WAKE port can be disabled by clearing bit WEN in the System Configuration register. ...
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... NXP Semiconductors 6.12 SPI interface The Serial Peripheral Interface (SPI) provides the communication link with the microcontroller, supporting multi-slave and multi-master operation. The SPI is configured for full duplex data transfer, so status information is returned when new control data is shifted in. The interface also offers a read-only access option, allowing registers to be read back by the application without changing the register content ...
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... NXP Semiconductors To protect against wrong or illegal SPI instructions, the SBC detects the following SPI failures: • SPI clock count failure (wrong number of clock cycles during one SPI access): only 16 clock periods are allowed during an SCS cycle. Any deviation from the 16 clock cycles results in an SPI failure interrupt, if enabled ...
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... NXP Semiconductors 6.12.3 Mode register The Mode register is used to define and re-trigger the watchdog and to select the SBC operating mode. The Mode register also contains the global enable output bit (EN) and the Software Development Mode (SDM) control bit. Cyclic access to the Mode register is required during system operation to serve the watchdog ...
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... NXP Semiconductors Table 6. Mode register bit description (bits Bit Symbol Description NWP[5:0] Nominal Watchdog Period WDPRE = 00 (as set in the Special Mode register) Nominal Watchdog Period WDPRE = 01 (as set in the Special Mode register) Nominal Watchdog Period WDPRE = 10 (as set in the Special Mode register) ...
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... NXP Semiconductors Table 6. Mode register bit description (bits Bit Symbol Description NWP[5:0] Nominal Watchdog Period WDPRE = 11 (as set in the Special Mode register) [1] The nominal watchdog periods are directly related to the SBC internal oscillator. The given values are valid for f [2] See Section 6 ...
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... NXP Semiconductors Table 7. System Status register bit description Bit Symbol Description RSS[3:0] Reset Source 7 CWS CAN Wake-up Status 6 - reserved 5 EWS Edge Wake-up Status 4 WLS WAKE Level Status 3 TWS Temperature Warning Status 2 SDMS Software Development Mode Status 1 ENS Enable Status 0 PWONS Power-on reset Status [1] The RSS bits are updated with each reset event and not cleared ...
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... NXP Semiconductors Table 8. System Diagnosis register bit description Bit Symbol Description 15 and 14 A1, A0 register address 13 RRS Read Register Select 12 RO Read Only 11 GSD Ground Shift Diagnosis CANFD [3:0] CAN Failure Diagnosis 6 and 5 - reserved 4 V3D V3 Diagnosis 3 V2D V2 Diagnosis 2 V1D V1 Diagnosis UJA1066_2 Product data sheet ...
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... NXP Semiconductors Table 8. System Diagnosis register bit description Bit Symbol Description 1 and 0 CANMD [1:0] CAN Mode Diagnosis [1] V2D will be set when V2 is reactivated after a failure. See 6.12.6 Interrupt Enable register and Interrupt Enable Feedback register These registers allow the SBC interrupt enable bits to be set, cleared and read back. ...
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... NXP Semiconductors Table 9. Interrupt Enable and Interrupt Enable Feedback register bit description Bit Symbol Description 3 WIE WAKE Interrupt Enable 2 WDRIE Watchdog Restart Interrupt Enable 1 CANIE CAN Interrupt Enable 0 - reserved [1] This bit is cleared automatically upon each overflow event. It has to be set in software each time the interrupt behavior is required (fail-safe behavior) ...
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... NXP Semiconductors Table 10. Interrupt register bit description Bit Symbol Description 15 and 14 A1, A0 register address 13 RRS Read Register Select 12 RO Read Only 11 WTI Watchdog Time-out Interrupt 10 OTI OverTemperature Interrupt 9 GSI Ground Shift Interrupt 8 SPIFI SPI clock count Failure Interrupt 7 BATFI BAT Failure Interrupt ...
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... NXP Semiconductors 6.12.8 System Configuration register and System Configuration Feedback register These registers are used to configure the behavior of the SBC. The settings can be read back. Table 11. System Configuration and System Configuration Feedback register bit description Bit Symbol Description 15 and 14 A1, A0 register address ...
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... NXP Semiconductors 6.12.9 Physical Layer Control register and Physical Layer Control Feedback register These registers are used to configure the CAN transceiver. The settings can be read back. Table 12. Physical Layer Control and Physical Layer Control Feedback register bit description Bit Symbol Description ...
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... NXP Semiconductors Table 13. Special Mode register and Special Mode Feedback register bit description Bit Symbol Description 15 and 14 A1, A0 register address 13 RRS Read Register Select 12 RO Read Only 11 and 10 - reserved 9 ISDM Initialize Software Development Mode 8 ERREM Error-pin Emulation Mode 7 - reserved 6 and 5 WDPRE [1:0] ...
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... NXP Semiconductors 6.12.11 General Purpose registers and General Purpose Feedback registers The UJA1066 contains two 12-bit General Purpose registers (and accompanying General Purpose Feedback registers) without predefined bit definitions. These registers can be used by the microcontroller for advanced system diagnosis or for storing critical system status information outside the microcontroller. After Power-up, General Purpose register 0 will contain a ‘ ...
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... NXP Semiconductors Table 16. System Status register: status at reset Symbol Name RSS reset source status CWS CAN wake-up status EWS edge wake-up status WLS WAKE level status TWS temperature warning status SDMS software development mode status ENS enable status PWONS power-on status [1] Depends on history ...
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... NXP Semiconductors Table 20. System Configuration register and System Configuration Feedback register: status at reset Symbol Name GSTHC GND shift level threshold control RLC reset length control V3C V3 control V1CMC V1 current monitor control WEN wake enable WSC wake sample control ILEN INH/LIMP enable ...
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... NXP Semiconductors Table 22. Special Mode register: status at reset Symbol Name ISDM initialize software development mode ERREM error pin emulation mode WDPRE watchdog prescale factor V1RTHC V1 reset threshold control Table 23. General Purpose register 0 and General Purpose Feedback register 0: status at reset Symbol Name ...
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... NXP Semiconductors To remain in Software development mode the SDM bit in the Mode register must be set each time the Mode register is accessed (i.e. watchdog triggering) regardless of how Software development mode was entered. Software development mode can be exited at any time by clearing the SDM bit in the Mode register ...
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... ESD performance according to IEC 61000-4 150 pF 330 Ω) of pins CANH, CANL, SPLIT, WAKE, BAT42 and V3 with respect [4] to GND was verified by an external test house. Following results were obtained: a) Equal or better than ±4 kV (unaided) b) Equal or better than ±20 kV (using external ESD protection: NXP Semiconductors PESD1CAN diode) Machine Model (MM 200 pF 0.75 μ Ω. [5] UJA1066_2 ...
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... NXP Semiconductors 8. Thermal characteristics Fig 13. Thermal model of the HTSSOP32 package 9. Static characteristics Table 26. Static characteristics − ° ° +150 5 BAT42 voltages are defined with respect to ground. Positive currents flow into the IC. Symbol Parameter Supply; pin BAT42 I BAT42 supply BAT42 current I additional BAT42 ...
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... NXP Semiconductors Table 26. Static characteristics − ° ° +150 5 BAT42 voltages are defined with respect to ground. Positive currents flow into the IC. Symbol Parameter Supply; pin BAT14 I BAT14 supply BAT14 current I additional BAT14 BAT14(add) supply current V BAT14 voltage level BAT14 Battery supply monitor input; pin SENSE ...
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... NXP Semiconductors Table 26. Static characteristics − ° ° +150 5 BAT42 voltages are defined with respect to ground. Positive currents flow into the IC. Symbol Parameter V undervoltage det(UV)(V1) detection and reset activation level V undervoltage rel(UV)(V1) detection release level V undervoltage level UV(VFI) for generating a VFI ...
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... NXP Semiconductors Table 26. Static characteristics − ° ° +150 5 BAT42 voltages are defined with respect to ground. Positive currents flow into the IC. Symbol Parameter I output current V2 capability V undervoltage det(UV)(V2) detection threshold Voltage source; pin BAT42-V3(drop) BAT42 V3 drop I overload current det(OL)(V3) detection threshold ⎪ ...
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... NXP Semiconductors Table 26. Static characteristics − ° ° +150 5 BAT42 voltages are defined with respect to ground. Positive currents flow into the IC. Symbol Parameter Serial peripheral interface data output; pin SDO I HIGH-level output OH current I LOW-level output OL current I OFF-state output OL(off) leakage current Reset output with clamping detection ...
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... NXP Semiconductors Table 26. Static characteristics − ° ° +150 5 BAT42 voltages are defined with respect to ground. Positive currents flow into the IC. Symbol Parameter High-speed CAN-bus lines; pins CANH and CANL V CANH dominant o(dom) output voltage CANL dominant output voltage V matching of o(m)(dom) ...
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... NXP Semiconductors Table 26. Static characteristics − ° ° +150 5 BAT42 voltages are defined with respect to ground. Positive currents flow into the IC. Symbol Parameter I recessive output o(reces) current R input resistance i R input resistance i(m) matching R differential input i(dif) resistance C common-mode input i(cm) ...
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... NXP Semiconductors Table 26. Static characteristics − ° ° +150 5 BAT42 voltages are defined with respect to ground. Positive currents flow into the IC. Symbol Parameter Temperature detection T high junction j(warn) temperature warning level All parameters are guaranteed over the virtual junction temperature range by design. Products are 100 % tested at 125 °C ambient [1] temperature on wafer level (pretesting). Cased products are 100 % tested at 25 ° ...
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... NXP Semiconductors Fig 14. V1 output voltage (dropout function of battery voltage UJA1066_2 Product data sheet ( −100 μA −50 mA −120 mA −250 ° ( −100 μA −50 mA −120 mA −250 150 °C. j All information provided in this document is subject to legal disclaimers. Rev. 03 — 17 March 2010 High-speed CAN fail-safe system basis chip ...
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... NXP Semiconductors I BAT14 (mA) (1) Types 5V0 and 3V3. (2) Type 5V0 only BAT14 (mA) (1) Types 5V0 and 3V3. (2) Types 3V3 only Fig 15. V1 quiescent current as a function of output current UJA1066_2 Product data sheet 10 − ( BAT14 2 (2) 5 −50 −100 0 = −40 °C, +25 °C and +150 °C. ...
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... NXP Semiconductors Fig 16. V1 output voltage as a function of output current PSRR (dB) (1) Type 5V0 only. Fig 17. V1 power supply ripple rejection as a function of frequency UJA1066_2 Product data sheet 6 type 5V0 V V1 (V) 4 type 3V3 2 0 − BAT14 = 25 °C to 125 ° 160 ...
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... NXP Semiconductors V BAT14 a. Line transient response (mA) b. Load transient response Fig 18. V1 transient response as a function of time UJA1066_2 Product data sheet 16 (V) V BAT14 100 200 = −5 mA μF; ESR = 0.01 Ω − − 100 200 = μF; ESR = 0.01 Ω BAT14 All information provided in this document is subject to legal disclaimers. ...
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... NXP Semiconductors ESR Fig 19. V1 output stability related to ESR value of output capacitor UJA1066_2 Product data sheet 1 (Ω) −1 10 −2 10 unstable operation area −3 10 −40 0 All information provided in this document is subject to legal disclaimers. Rev. 03 — 17 March 2010 High-speed CAN fail-safe system basis chip stable operation area − ...
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... NXP Semiconductors a. Switch-on test circuit. b. Behavior Behavior at T Fig 20. Switch-on behavior of V UJA1066_2 Product data sheet BAT42 BAT14 100 μF/ V BAT 0.1 Ω 100 ( BAT V = 5.5 V BAT BAT ° ( BAT 5.5 V BAT BAT ° All information provided in this document is subject to legal disclaimers. ...
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... NXP Semiconductors 10. Dynamic characteristics Table 27. Dynamic characteristics − ° ° +150 5 BAT42 voltages are defined with respect to ground. Positive currents flow into the IC. Symbol Parameter Serial peripheral interface timing; pins SCS, SCK, SDI and SDO (see T clock cycle time cyc t enable lead time ...
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... NXP Semiconductors Table 27. Dynamic characteristics − ° ° +150 5 BAT42 voltages are defined with respect to ground. Positive currents flow into the IC. Symbol Parameter t maximum time before off-line entering Off-line mode t extended minimum time off-line(ext) before entering Off-line mode Battery monitoring t BAT42 LOW time for setting ...
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... NXP Semiconductors Table 27. Dynamic characteristics − ° ° +150 5 BAT42 voltages are defined with respect to ground. Positive currents flow into the IC. Symbol Parameter Reset output; pin RSTN t clamped HIGH time, RSTN(CHT) pin RSTN t clamped LOW time, RSTN(CLT) pin RSTN t interrupt monitoring time ...
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... NXP Semiconductors Fig 22. Timing test circuit for CAN transceiver Fig 23. Timing diagram CAN transceiver 11. Test information 11.1 Quality information This product has been qualified to the appropriate Automotive Electronics Council (AEC) standard Q100 or Q101 and is suitable for use in automotive applications. UJA1066_2 Product data sheet ...
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... NXP Semiconductors 12. Package outline HTSSOP32: plastic thermal enhanced thin shrink small outline package; 32 leads; body width 6.1 mm; lead pitch 0.65 mm; exposed die pad y exposed die pad side pin 1 index 1 e DIMENSIONS (mm are the original dimensions). A UNIT max. 0.15 0.95 mm 1.1 0.25 ...
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... NXP Semiconductors 13. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 13.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...
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... NXP Semiconductors 13.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • ...
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... NXP Semiconductors Fig 25. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. UJA1066_2 Product data sheet maximum peak temperature = MSL limit, damage level temperature minimum peak temperature = minimum soldering temperature MSL: Moisture Sensitivity Level All information provided in this document is subject to legal disclaimers ...
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... NXP Semiconductors 14. Revision history Table 30. Revision history Document ID Release date UJA1066_3 20100317 • Modifications: Error in UJA1066_2 20090505 UJA1066_1 20070424 UJA1066_2 Product data sheet Data sheet status Product data sheet Figure 20 corrected Product data sheet Objective data sheet All information provided in this document is subject to legal disclaimers. ...
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... NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. ...
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... NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any 16. Contact information For more information, please visit: ...
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... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 2 2.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.2 CAN transceiver . . . . . . . . . . . . . . . . . . . . . . . . 2 2.3 Power management . . . . . . . . . . . . . . . . . . . . . 3 2.4 Fail-safe features . . . . . . . . . . . . . . . . . . . . . . . 3 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 4 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 Functional description . . . . . . . . . . . . . . . . . . . 7 6.1 Introduction 6.2 Fail-safe system controller . . . . . . . . . . . . . . . . 7 6 ...
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... NXP Semiconductors 16 Contact information Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 High-speed CAN fail-safe system basis chip Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2010. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp ...