UJA1066TW/5V0,518 NXP Semiconductors, UJA1066TW/5V0,518 Datasheet - Page 12

• Manufacturer Part Number: UJA1066TW/5V0,518
• Manufacturer: NXP Semiconductors

Specifications of UJA1066TW/5V0,518

• Number Of Transceivers: 1
• Power Down Mode: Sleep/Standby
• Standard Supported: ISO 11898-2
• Operating Supply Voltage (min): 5.5V
• Operating Temperature (max): 125C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

NXP Semiconductors
UJA1066_2
Product data sheet
6.3 On-chip oscillator
6.4 Watchdog
Once in Start-up mode the application software has to write Operating Mode code 011 to
the Mode register within t
successfully received hardware reset (handshake between the SBC and the
microcontroller) to be fed back. The transition from Start-up mode to Flash mode can only
occur once after the Flash entry sequence has been completed.
The application can choose not to enter Flash mode but instead return to Normal mode by
using the Operating Mode code 101 for handshaking. This erases the Flash mode entry
sequence.
The watchdog behavior in Flash mode is similar to its time-out behavior in Standby mode,
but Operating Mode code 111 must be used for serving the watchdog. If this code is not
used or if the watchdog overflows, the SBC will immediately force a reset and a transition
to Start-up mode. Operating Mode code 110 (leave Flash mode) is used to correctly exit
Flash mode. This results in a system reset with the corresponding reset source
information. Other Mode register codes will cause a forced reset with reset source code
‘illegal Mode register code’.
The on-chip oscillator provides the clock signal for all digital functions and is the timing
reference for the on-chip watchdog and the internal timers.
If the on-chip oscillator frequency is too low or the oscillator is not running at all, there is
an immediate transition to Fail-safe mode. The SBC will stay in Fail-safe mode until the
oscillator has recovered to its normal frequency and the system receives a wake-up
event.
The watchdog provides the following timing functions:
The watchdog is clocked directly by the on-chip oscillator.
To guarantee fail-safe control of the watchdog via the SPI, all watchdog accesses are
coded with redundant bits. Therefore, only certain codes are allowed for a proper
watchdog service.
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Start-up mode; needed to give the software the opportunity to initialize the system
Window mode; detects ‘too early’ and ‘too late’ accesses in Normal mode
Time-out mode; detects a ‘too late’ access, can also be used to restart or interrupt the
microcontroller from time to time (cyclic wake-up function)
OFF mode; fail-safe shutdown during operation prevents any blind spots occurring in
the system supervision
All information provided in this document is subject to legal disclaimers.
Rev. 03 — 17 March 2010
WD(init)
to initiate a transition to Flash mode. This causes a
High-speed CAN fail-safe system basis chip
UJA1066
© NXP B.V. 2010. All rights reserved.
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