UJA1066TW/5V0,518 NXP Semiconductors, UJA1066TW/5V0,518 Datasheet - Page 11

• Manufacturer Part Number: UJA1066TW/5V0,518
• Manufacturer: NXP Semiconductors

Specifications of UJA1066TW/5V0,518

• Number Of Transceivers: 1
• Power Down Mode: Sleep/Standby
• Standard Supported: ISO 11898-2
• Operating Supply Voltage (min): 5.5V
• Operating Temperature (max): 125C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

NXP Semiconductors
UJA1066_2
Product data sheet
6.2.6 Sleep mode
6.2.7 Flash mode
In Sleep mode the microcontroller power supply (V1) and the INH/LIMP-controlled
external supplies are switched off entirely, resulting in minimum system power
consumption. In this mode, the watchdog runs in Time-out mode or is completely off.
Entering Sleep mode results in an immediate LOW level on pin RSTN, stopping all
microcontroller operations. The INH/LIMP output is floating in parallel and pin V1 is
disabled. Only pin SYSINH can remain active to support the V2 voltage supply (if bit V2C
is set; see
wake-up switches.
If the watchdog is not disabled by software, it will continue to run and will force a system
reset once the programmed watchdog period has expired. The SBC then enters Start-up
mode and pin V1 becomes active again. This behavior can be used to implement cyclic
wake-up from Sleep mode.
Depending on the application, the following operations can be selected from Sleep mode:
Flash mode can only be entered from Normal mode by entering a specific Flash mode
entry sequence. This fail-safe control sequence comprises three consecutive write
accesses to the Mode register, within the legal windows of the watchdog, using the
operating mode codes 111, 001 and 111 respectively. Once this sequence has been
received, the SBC will enter Start-up mode and perform a system reset using the related
reset source information (bits RSS[3:0] = 0110).
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Cyclic wake-up by the watchdog via an interrupt signal to the microcontroller (the
microcontroller is triggered periodically and checked for the correct response)
Cyclic wake-up by the watchdog via a reset signal (a reset is performed periodically;
the SBC provides information about the reset source to allow different start
sequences after reset)
Wake-up by activity on the CAN-bus via an interrupt signal to the microcontroller
Wake-up by bus activity on the CAN-bus via a reset signal
Wake-up by increasing the microcontroller supply current without a reset signal
(where a stable supply is needed for the microcontroller RAM contents to remain valid
and wake-up from an external application not connected to the SBC)
Wake-up by increasing the microcontroller supply current with a reset signal
Wake-up due to a falling edge at pin WAKE forcing an interrupt to the microcontroller
Wake-up due to a falling edge at pin WAKE forcing a reset signal
Cyclic wake-up by the watchdog (only in Time-out mode); a reset is performed
periodically, the SBC provides information about the reset source to allow the
microcontroller to choose between different start up sequences after reset
Wake-up by activity on the CAN-bus or falling edge on pin WAKE
An overload on V3, only if V3 is in a cyclic or a continuously ON mode
Table
All information provided in this document is subject to legal disclaimers.
12). V3 can also be ON, OFF or in Cyclic mode to supply external
Rev. 03 — 17 March 2010
High-speed CAN fail-safe system basis chip
UJA1066
© NXP B.V. 2010. All rights reserved.
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